One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Methods and apparatus to provide welding power are disclosed. An example welding-type power supply includes: a transformer having first and second secondary windings; switching elements configured to control current flow from the first and second secondary windings to an output; and a control circuit configured to control the switching elements to selectively output a positive output voltage or a negative output voltage without a separate rectifier stage by selecting, based on an output voltage polarity, a first subset of the switching elements to perform rectification.

In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

A circuit arrangement, a semiconductor module, an electrical system, and a method for optically outputting information using a MOSFET. The circuit arrangement includes a MOSFET with an optical interface and a gate control circuit. The optical interface is configured to guide light, generated by an inverse diode of the MOSFET, into surroundings of the MOSFET. The gate control circuit is configured to receive an input signal representing information to be output using the circuit arrangement, and to generate from the input signal an output signal representing the information to be output. The gate control circuit varies the gate-source voltage of the MOSFET in a reverse mode of the MOSFET based on the output signal to vary a light emission of the inverse diode of the MOSFET in a corresponding manner, so that an output of the information to be output takes place via the optical interface of the MOSFET.

A device and structure for providing electrostatic discharge (ESD) protection. Schottky barrier diode (SBD) structure comprising a substrate of a first dopant polarity, a well region of a second dopant polarity formed on or within said substrate, an anode region of a first dopant polarity, a cathode of a second polarity, and a rectifying contact on said anode and/or said cathode, wherein said rectifying contact is formed substantially near the surface of said substrate to provide a rectifying barrier junction between the conducting layer and the semiconductor substrate, providing electrical coupling in said Schottky Barrier diode structure. The disclosure further includes SOI Schottky Barrier polysilicon-bound diodes (also known as Lubistor structures). Additionally, a diode configured SOI dynamic threshold MOSFET with rectifying barrier junctions on the drain or source region.

CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.

Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.