An example welding-type power supply includes: a transformer having a primary winding and first and second secondary windings; an input circuit configured to provide an input voltage to the primary winding of the transformer; first, second, third, and fourth switching elements, and a control circuit configured to: control the first, second, third, and fourth switching elements to selectively output a positive or negative output voltage without a separate rectifier stage by selectively controlling ones of the first, second, third, and fourth switching elements based on a commanded output voltage polarity and an input voltage polarity to the transformer; and prior to changing from a first output voltage polarity to a second output voltage polarity, controlling the first, second, third, and fourth switching elements to reverse the power flow to return reactive energy to an input circuit via the transformer.

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.