Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

An apparatus includes a substrate and a transistor disposed on the substrate. The transistor includes a source and a source contact disposed on the source. The transistor also includes a drain and a drain contact disposed on the drain. A gate is disposed between the source contact and the drain contact, and a screened region is disposed adjacent the source contact or the drain contact. The screened region corresponds to a lightly doped region. The screened region includes an implant screen configured to reduce an effective dose in the screened region so as to shift an acceptable dose range of the screened region to a higher dose range. The acceptable dose range corresponds to acceptable breakdown voltage values for the screened region.

The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.

A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.