A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer formed adjacent the first gate structure, and first conductive source/drain contact structures positioned adjacent the first gate structure and separated from the first gate structure by the first spacer. A first portion of the first conductive source/drain contact structures is recessed at a first axial position along the first gate structure to define a first cavity. A second portion of the first conductive source/drain contact structures is recessed at a second axial position along the gate structure to define a second cavity. A dielectric cap layer is formed in the first and second cavities. A first conductive contact contacting the first gate structure in the first axial position is formed.

A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the second conductivity type, connected with the first semiconductor region; a first electrode forming a Schottky contact with a first semiconductor layer and a first semiconductor region; and a second electrode forming an ohmic contact with the second semiconductor region. A density of the second electrode is lower at a center portion of the silicon carbide semiconductor substrate and increases toward an outer peripheral side.

In one general aspect, a device can include a first trench disposed in a semiconductor region, a second trench disposed in the semiconductor region, and a recess disposed in the semiconductor region between the first trench and the second trench. The recess has a sidewall and a bottom surface. The device also includes a Schottky interface along a sidewall of the recess and the bottom surface of the recess excludes a Schottky interface.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

A reconfigurable field effect transistor (RFET) includes a nanowire, wherein the nanowire comprises two Schottky contacts, as well as two gate contacts partially enclosing the nanowire in cross section. An integrated circuit can be produced therefrom. The aim of producing CMOS circuits with enhanced functionality and a more compact design is achieved in that the nanowire is divided along the cross section thereof into two nanowire parts, wherein each nanowire part comprises a respective Schottky contact and a respective gate contact, and the two nanowire parts are connected electrically to one another via a common substrate and stand vertically on the substrate. In a nanowire-parts-array, between the nanowire parts, a respective top-gate contact and/or back-gate contact can be formed in a substrate defining a substrate plane.

According to one embodiment, a semiconductor device include first to third electrode, a semiconductor member, a first conductive member, and a first insulating member. A second insulating region of the first insulating member includes a first face facing the third partial region of the first semiconductor region. The third insulating region of the first insulating member includes a second face facing the third partial region of the first semiconductor region. The first face includes a first end on a side of the first electrode in the first direction. The second face includes a second end on a side of the second electrode in the first direction. A second position of the second end in the second direction is different from a first position of the first end in the second direction.