An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Methods of synthesis and fabrication of a transition metal dichalcogenide (TMD) structures are disclosed. A method can include first patterning a transition metal (TM) on a substrate and placing the substrate in a process chamber. Oxygen can be applied to the transition metal on the substrate and a mixture of highly reactive transition metal oxides can be formed and simultaneously thinned down by sublimation. Finally, a chalcogen can be applied to the substrate and a transition metal dichalcogenide structure can be formed.

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

A Schottky contact structure for a semiconductor device having a Schottky contact and an electrode for the contact structure disposed on the contact. The Schottky contact comprises: a first layer of a first metal in Schottky contact with a semiconductor; a second layer of a second metal on the first layer; a third layer of the first metal on the second layer; and a fourth layer of the second metal on the third layer. The electrode for the Schottky contact structure disposed on the Schottky contact comprises a third metal, the second metal providing a barrier against migration between the third metal and the first metal.

Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.