A method for producing an ohmic contact on a crystallographic C-side of a silicon carbide substrate. The method includes: applying a layer stack to the crystallographic C-side of the silicon carbide substrate, the layer stack including at least one semiconducting layer containing germanium, and at least one metallic layer; and producing a point-by-point liquid phase of the layer stack, a surface of the layer stack being scanned using laser beams.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

A semiconductor device with a high on-state current is provided. An oxide semiconductor film; a source electrode and a drain electrode over the oxide semiconductor film; an interlayer insulating film positioned to cover the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the oxide semiconductor film; a barrier insulating film over the oxide semiconductor film; and a gate electrode over the gate insulating film are included. The barrier insulating film is positioned between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are positioned in the opening of the interlayer insulating film. Above the barrier insulating film, the gate insulating film is in contact with the interlayer insulating film.

To provide a highly reliable memory device. A first insulator is formed over a substrate; a second insulator is formed over the first insulator; a third insulator is formed over the second insulator; an opening penetrating the first insulator, the second insulator, and the third insulator is formed; a fourth insulator is formed on the inner side of a side surface of the first insulator, a side surface of the second insulator, and a side surface of the third insulator, in the opening; an oxide semiconductor is formed on the inner side of the fourth insulator; the second insulator is removed; and a conductor is formed between the first insulator and the third insulator; and the fourth insulator is formed by performing, a plurality of times, a cycle including a first step of supplying a gas containing silicon and an oxidizing gas into a chamber where the substrate is placed, a second step of stopping the supply of the gas containing silicon into the chamber; and a third step of generating plasma containing the oxidizing gas in the chamber.

A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

Cross-coupled structures are provided. Cross-coupled structures may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, and the fourth transistor may be spaced apart from each other in a first direction, and the third transistor and the second transistor may be stacked in a second direction that is perpendicular to the first direction. The third transistor and the second transistor may include a common gate structure, a first portion of the common gate structure may be a gate structure of the second transistor, and a second portion of the common gate structure may be a gate structure of the third transistor.

Techniques are provided to form semiconductor devices having a multi-layer spacer structure. In an example, a semiconductor device includes a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor region. A spacer structure made up of one or more dielectric layers is present along a sidewall of the gate structure and along a sidewall of the source region or the drain region. The spacer structure has three different portions: a first portion along the sidewall of the gate, a second portion along the sidewall of the source or drain region, and a third portion that connects between the first two portions. The third portion of the spacer structure has a multi-layer configuration while the first and second portions have a fewer number of material layers.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; during the write operation after the page erase operation, the positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line; and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.