A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

A dual-floating gates optoelectronic self-exciting synaptic memristor includes a bottom gate, a barrier layer coated on a surface of the bottom gate, a quantum dot layer coated on a surface of a middle portion of the barrier layer, two inverted L-shaped electron or hole tunneling layers coated on a surface of two end portions of the quantum dot layer respectively, two inverted L-shaped floating gate storage layers coated on the electron or hole tunneling layers respectively, two electron or hole blocking layers coated on the two floating gate storage layers respectively, an inverted L-shaped source electrode and an inverted L-shaped drain electrode coated on the two electron or hole blocking layers respectively, a photosensitive material layer coated on a surface of a middle portion of the quantum dot layer, and a top gate coated on the photosensitive material layer.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.