A nitride semiconductor device having a field effect gate is disclosed. The disclosed nitride semiconductor device includes a high-resistance material layer including a Group III-V compound semiconductor, a first channel control layer on the high-resistance material layer and including a Group III-V compound semiconductor of a first conductivity type, a channel layer on the channel layer control layer and including a nitride semiconductor of a second conductivity type opposite to the first conductivity type, and a gate electrode having a contact of an ohmic contact type with the first channel control layer.

A nitride semiconductor device having a field effect gate is disclosed. The disclosed nitride semiconductor device includes a high-resistance material layer including a Group III-V compound semiconductor, a first channel control layer on the high-resistance material layer and including a Group III-V compound semiconductor of a first conductivity type, a channel layer on the channel layer control layer and including a nitride semiconductor of a second conductivity type opposite to the first conductivity type, and a gate electrode having a contact of an ohmic contact type with the first channel control layer.

A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

A semiconductor device having, in a plan view thereof, an active region and a termination region that surrounds a periphery of the active region. The device includes a semiconductor substrate containing a wide bandgap semiconductor, a first-conductivity-type region provided in the semiconductor substrate, spanning from the active region to the termination region, a plurality of second-conductivity-type regions provided between the first-conductivity-type region and the first main surface of the semiconductor substrate in the active region, a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the second-conductivity-type regions, a second electrode provided on the second main surface of the semiconductor substrate and electrically connected to the first-conductivity-type region, and a lifetime killer region provided in the first-conductivity-type region and spanning from the active region to the termination region. In the active region, pn junctions between the first-conductivity-type region and the second-conductivity-type regions form a vertical semiconductor device element.

A semiconductor device having, in a plan view thereof, an active region and a termination region that surrounds a periphery of the active region. The device includes a semiconductor substrate containing a wide bandgap semiconductor, a first-conductivity-type region provided in the semiconductor substrate, spanning from the active region to the termination region, a plurality of second-conductivity-type regions provided between the first-conductivity-type region and the first main surface of the semiconductor substrate in the active region, a first electrode provided on a first main surface of the semiconductor substrate and electrically connected to the second-conductivity-type regions, a second electrode provided on the second main surface of the semiconductor substrate and electrically connected to the first-conductivity-type region, and a lifetime killer region provided in the first-conductivity-type region and spanning from the active region to the termination region. In the active region, pn junctions between the first-conductivity-type region and the second-conductivity-type regions form a vertical semiconductor device element.

A semiconductor device is provided, which includes a semiconductor chip; a first current input/output portion that is electrically connected to the semiconductor chip; a second current input/output portion that is electrically connected to the semiconductor chip; three or more conducting portions provided with the semiconductor chip, between the first current input/output portion and the second current input/output portion; and a current path portion having a path through which current is conducted to each of the three or more conducting portions, wherein the current path portion includes a plurality of slits.

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.