A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.

A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

Provided is a semiconductor device with higher reliability and longer life which can suppress an increase in production costs. A semiconductor device includes: a semiconductor element; a top electrode on an upper surface of the semiconductor element; and a conductive metal plate containing copper as a main component and solid-state diffusion bonded to the top electrode of the semiconductor element.

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.