A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.

The present invention provides an OLED display panel and a manufacturing method thereof. The OLED display panel comprises a display area and a bonding area defined at least at one side of the display area. The OLED display panel further comprises a substrate and a first metal layer disposed on the substrate. The first metal layer comprises a light-shielding metal disposed corresponding to the display area and a bonding metal disposed corresponding to the bonding area.

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.