A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.