A multi-chip package (MCP) includes semiconductor chips integrated therein. Each semiconductor chip includes: pad groups which extend in a first direction and are arranged in a second direction, and each of which includes a first metal line and a second metal line that are stacked in a third direction with an interlayer dielectric layer interposed therebetween; receivers which one-to-one correspond to the respective pad groups, and each of which includes a first input terminal coupled with the first metal line of a corresponding pad group, and an output terminal coupled with the second metal line of the corresponding pad group; and selectors, each of which selects one of a feedback signal transferred from the output terminal of a corresponding receiver and a reference voltage, and provides the selected one to a second input terminal of the corresponding receiver, in response to a chip select signal.

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.

A semiconductor chip may include a semiconductor substrate, a first central pad, a second central pad, a first peripheral pad, a second peripheral pad, a first pad line and a second pad line. The semiconductor substrate may have an active face. The first central pad and the second central pad may be arranged on a central region of the active face. The first peripheral pad and the second peripheral pad may be arranged on an edge region of the active face. The first pad line may be connected between the first central pad and the first peripheral pad. The second pad line may be connected between the second central pad and the second peripheral pad.

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.

A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.