A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.

A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.

A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

The connection method between at least two elements (E1, E2) corresponding to a printed circuit (4) and to an electronic component (5), comprises a step of forming a plurality of pad-type stacks (2) of bosses (3), the stacks (2) of bosses (3) being formed on a face (10) of a first (E1) of the elements (E1, E2), the stacks (2) of bosses (3) each comprising the same given number of bosses (3), said method also comprising a step of depositing a brazing product (7) on this first element (E1) provided with stacks (2) of bosses (3), a step of arranging the second (E2) of the elements (E1, E2) on the first element (E1), and a step of remelting the assembly thus formed, in order to obtain an electronic device (1). This method makes it possible to produce a precise and flexible raising of surface mounted electronic components.

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.