Patent classifications
H01L2224/27318
Air cavity packages and methods for the production thereof
Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.
High reliability wafer level semiconductor packaging
Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.
Packaged IC With Solderable Sidewalls
A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE
A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.
Packaged IC with solderable sidewalls
A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
INKJET ADHESIVE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC COMPONENT
Provided is an inkjet adhesive which is applied using an inkjet device, wherein the adhesive can suppress generation of voids in the adhesive layer and, after bonding, can reduce an outgas at the time of being exposed to high temperatures, and can enhance moisture-resistant reliability. An inkjet adhesive according to the present invention comprises a first photocurable compound having one (meth)acrylol group, a second photocurable compound having two or more (meth)acrylol groups, a photo-radical initiator, a thermosetting compound having one or more cyclic ether groups or cyclic thioether groups, and a compound capable of reacting with the thermosetting compound, and the first photocurable compound contains alkyl (meth)acrylate having 8 to 21 carbon atoms.
METHODS FOR BONDING SUBSTRATES
Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.
METHODS FOR BONDING SUBSTRATES
Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.
METHOD FOR FABRICATING STACK DIE PACKAGE
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.
METHOD FOR FABRICATING STACK DIE PACKAGE
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.