H01L2224/27318

Integrated circuit package and method of making same

A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

Method for fabricating stack die package
09589929 · 2017-03-07 · ·

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Method for fabricating stack die package
09589929 · 2017-03-07 · ·

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Semiconductor packaging containing sintering die-attach material

Sintering die-attach materials provide a lead-free solution for semiconductor packages with superior electrical, thermal and mechanical performance to prior art alternatives. Wafer-applied sintering materials form a metallurgical bond to both semiconductor die and adherends as well as throughout the die-attach joint and do not remelt at the original process temperature. Application to either one or both sides of the wafer, as well as paste a film application are disclosed.

Semiconductor packaging containing sintering die-attach material

Sintering die-attach materials provide a lead-free solution for semiconductor packages with superior electrical, thermal and mechanical performance to prior art alternatives. Wafer-applied sintering materials form a metallurgical bond to both semiconductor die and adherends as well as throughout the die-attach joint and do not remelt at the original process temperature. Application to either one or both sides of the wafer, as well as paste a film application are disclosed.

Fan out system in package and method for forming the same
09583472 · 2017-02-28 · ·

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

Semiconductor device and method for manufacturing the same
12288739 · 2025-04-29 · ·

A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20250226296 · 2025-07-10 ·

A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.

Semiconductor Device and Method of Forming AIP Package Structure from Separate Assemblies with Bonding Material

A semiconductor device has a semiconductor assembly and an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly. A bonding material is disposed between the antenna substrate and semiconductor assembly. An encapsulant is deposited over the antenna substate. The encapsulant may be planar or have encapsulant bumps. The bonding material extends over a side surface of the antenna substrate. The antenna substrate has a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly. The first antenna substrate is offset with respect to the second antenna substrate in the horizontal and/or vertical directions. The antenna substrate can fan out from the semiconductor assembly. The semiconductor assembly can have multiple layers of core material with different coefficient of thermal expansions. A heat sink or shielding layer can be formed over the antenna substrate and semiconductor assembly.

METHOD FOR DIE BONDING AN LED CHIP

A method for die bonding an LED chip includes S1: forming a preset adhesive droplet array corresponding to one pad on a substrate based on the area S of one LED chip and the radius R of an adhesive droplet formed by a dispensing device in a single dispensing action, where parameters of the preset adhesive droplet array include the number X of adhesive droplets in a horizontal direction, the number Y of adhesive droplets in a vertical direction, and a horizontal distance H between two horizontally adjacent adhesive droplets, and a vertical distance D between two vertically adjacent adhesive droplets; S2: dispensing a conductive adhesive onto the pad multiple times according to the preset adhesive droplet array to form a bonding portion; and S3: placing the LED chip on the bonding portion and curing the conductive adhesive.