A method for manufacturing a module including N layers of stacked resin is provided, wherein N is a natural number of two or more. In the method, resin of a first layer is cured to a degree that does not fully harden the resin of the first layer. Resin of a Mth layer is stacked on resin of a (M1)th layer, wherein M is a natural number of two or more and less than N. The resin of the Mth layer is cured to a degree that does not fully harden the resin of the Mth layer. Stacking the resin of the Mth layer and curing the resin of the Mth layer are repeated. Then, resin of Nth layer is stacked, and all of the N layers of stacked resin are fully hardened.

The present invention relates to a conductive paste for bonding comprising 100 parts by weight of the metal powder, 5 to 20 parts by weight of a solvent, and 0.05 to 3 parts by weight of a polymer, wherein the polymer comprises a first polymer and a second polymer, wherein the molecular weight (Mw) of the first polymer is 5,000 to 95,000, and the molecular weight (Mw) of the second polymer is 100,000 to 300,000.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

A method for producing a layer including a connecting medium on an assembly partner is provided. The method includes providing a carrier on which the connecting medium is applied. The connecting medium contains a metal in the form of a multiplicity of metal particles. The assembly partner is placed on the connecting medium located on the carrier and pressed onto the connecting medium located on the carrier, so that a layer of the connecting medium adheres to the assembly partner. The assembly partner together with the layer adhering thereto is removed from the carrier. By means of a gas flow, edges of the layer, at which the latter extends laterally beyond the assembly partner, are removed so that a layer residue of the layer remains adhering to the assembly partner.

The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused.

A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused.

The present disclosure A heat dissipation substrate includes: a metal-ceramic composite board, where the metal-ceramic composite board is a metal layer wrapping a ceramic body; a metal oxide layer integrated with the metal layer and formed on an outer surface of the metal layer; and a conductive layer formed on at least a part of an outer surface of the metal oxide layer, where a conductive trace is formed on the conductive layer, and is used to connect with and bear a chip.

The present disclosure A heat dissipation substrate includes: a metal-ceramic composite board, where the metal-ceramic composite board is a metal layer wrapping a ceramic body; a metal oxide layer integrated with the metal layer and formed on an outer surface of the metal layer; and a conductive layer formed on at least a part of an outer surface of the metal oxide layer, where a conductive trace is formed on the conductive layer, and is used to connect with and bear a chip.

A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.