A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

The present invention discloses a substrate configured to receive a plurality of micro elements on a carrier board. The substrate comprises a body, a first conductive bump, and a second conductive bump. The body has a first surface, a transfer area is defined within the first surface, and a central portion and a peripheral portion is defined within the transfer area. The first conductive bump, disposed on the central portion, has a first volume. The second conductive bump, disposed on the peripheral portion, has a second volume. Wherein the first volume is different from the second volume.

The present invention discloses a substrate configured to receive a plurality of micro elements on a carrier board. The substrate comprises a body, a first conductive bump, and a second conductive bump. The body has a first surface, a transfer area is defined within the first surface, and a central portion and a peripheral portion is defined within the transfer area. The first conductive bump, disposed on the central portion, has a first volume. The second conductive bump, disposed on the peripheral portion, has a second volume. Wherein the first volume is different from the second volume.

An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including ≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.