A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

Embodiments may relate to a microelectronic package that includes a package substrate and a signal interconnect coupled with the face of the package substrate. The microelectronic package may further include a ground interconnect coupled with the face of the package substrate. The ground interconnect may at least partially surround the signal interconnect. Other embodiments may be described or claimed.

A semiconductor substrate (1) has a front surface and a back surface that are opposite each other. A first metal layer (2) is formed on the front surface of the semiconductor substrate (1). A second metal layer (3) for soldering is formed on the first metal layer (2). A third metal layer (5) is formed on the back surface of the semiconductor substrate (1). A fourth metal layer (6) for soldering is formed on the third metal layer (5). The second metal layer (3) has a larger thickness than that of the fourth metal layer (6). The first, third, and fourth metal layers (2,5,6) are not divided in a pattern. The second metal layer (3) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer (2).

A semiconductor package includes a package substrate, an image sensor disposed on the package substrate, and a bonding layer disposed between the package substrate and the image sensor, and including a first region and a second region, the second region has a modulus of elasticity lower than that of the first region and is disposed on a periphery of the first region.

A semiconductor substrate (1) has a front surface and a back surface that are opposite each other. A first metal layer (2) is formed on the front surface of the semiconductor substrate (1). A second metal layer (3) for soldering is formed on the first metal layer (2). A third metal layer (5) is formed on the back surface of the semiconductor substrate (1). A fourth metal layer (6) for soldering is formed on the third metal layer (5). The second metal layer (3) has a larger thickness than that of the fourth metal layer (6). The first, third, and fourth metal layers (2, 5, 6) are not divided in a pattern. The second metal layer (3) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer (2).

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.

An integrated circuit package includes at least one electronic chip having a first face fastened onto a first face of a carrier substrate by an adhesive interface. The adhesive interface includes a crown formed of a first adhesive material that is fastened on the periphery of the first face of the electronic chip. The crown defining an internal housing. A second adhesive material, different than the first material, is deposited in the internal housing.