A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.

A semiconductor device includes an electrode having a flat part and a non-flat part made up of a concave part, a joint layer being made of a sintered body of metal crystal grains provided on the flat part and the non-flat part of the electrode, and a semiconductor element being joined to the electrode with the joint layer therebetween, wherein the joint layer has a first region sandwiched between the non-flat part and the semiconductor element and a second region sandwiched between the flat part and the semiconductor element, and either one of the first region and the second region having a larger film thickness has a filling rate of the metal crystal grains smaller than the other one of the first region and the second region having a smaller film thickness. The present invention enhances reliability of a joint layer made of a sintered body of metal crystal grains.

An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

An integrated circuit assembly may be formed comprising at least one integrated circuit device, a heat dissipation device having a thermal contact surface with at least one containment structure extending into or from the heat dissipation device at the thermal contact surface, and a thermal interface material between the at least one integrated circuit device and the heat dissipation device, wherein the thermal interface material contacts the at least one containment structure of the heat dissipation device.

A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.

A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.

The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100° C., preferably at most 60° C., advantageously at most 20° C. and ideally at most 5° C. and/or deviates from the operating temperature of the component by at most 50° C., preferably by at most 20° C., in particular by at most 10° C. and ideally by at most 5° C., preferably by at most 2° C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

A light-emitting apparatus includes a substrate, pads disposed on the substrate, a sacrificial pattern layer and a light-emitting diode element disposed on the sacrificial pattern layer. The light-emitting diode element includes a first type semiconductor layer, a second type semiconductor layer, an active layer, and electrodes. A connection patterns disposed on at least one of the electrodes and the pads. Materials of the connection patterns include hot fluidity conductive materials. The connection patterns cover an outermost sidewall of the sacrificial pattern layer and are electrically connected to the at least one of the electrodes and the pads. The sacrificial pattern layer is located between the connection patterns, and the sacrificial pattern layer is overlapped with the pads in a normal direction of the substrate.

A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.