One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

In some examples, a system comprises a first component having a first surface, a first set of nanoparticles coupled to the first surface, and a first set of nanowires extending from the first set of nanoparticles. The system also comprises a second component having a second surface, a second set of nanoparticles coupled to the second surface, and a second set of nanowires extending from the second set of nanoparticles. The system further includes an adhesive positioned between the first and second surfaces. The first and second sets of nanowires are positioned within the adhesive.

A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.

A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.

A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.

A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.