A method for forming a semiconductor structure includes receiving a first die having a first interconnect structure and a first bonding layer over the first interconnect structure, and a second die having a second interconnect structure and a second bonding layer over the second interconnect structure; forming a recess indenting into the first bonding layer; and forming a positioning member on the second bonding layer. The method further includes bonding the second die over the first die; and disposing the positioning member into the recess. The positioning member includes dielectric, is surrounded by the first bonding layer, and is isolated from the first interconnect structure and the second interconnect structure.

A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

In one embodiment, a power semiconductor module includes a main substrate, semiconductor chips mounted on the main substrate, and an auxiliary substrate also mounted on the main substrate. The power semiconductor module is capable of handling a current of 10 A or more. The auxiliary substrate is a printed circuit board having at least one carrier layer that is based on an organic material. The auxiliary substrate provides a common contact platform for at least some of the first semiconductor chips. The auxiliary substrate is attached to the main substrate by a joining layer located at a bottom side of the at least one auxiliary substrate facing the main substrate. The joining layer is a continuous organic adhesive layer of an adhesive foil or a double-faced adhesive tape.

A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.

A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.

A power inverter module includes a base module having a plurality of electrically conductive layers, including a first conductive layer, a second conductive layer and a third conductive layer. A first terminal is operatively connected to the first conductive layer at a first end and a second terminal is operatively connected to the second conductive layer at the first end. An isolation sheet is sandwiched between the first and second terminals. The first terminal and the second terminal include a respective proximal portion composed of a first material and a respective distal portion composed of a second material. At least one of the first terminal and the second terminal is bent to create an overlap zone such that a gap between the first terminal and the second terminal in the overlap zone is less than a threshold distance. The power inverter module is configured to reduce parasitic inductance.

A method for forming a semiconductor structure includes receiving a first die having a first interconnect structure and a first bonding layer over the first interconnect structure, and a second die having a second interconnect structure and a second bonding layer over the second interconnect structure; forming a recess indenting into the first bonding layer; and forming a positioning member on the second bonding layer. The method further includes bonding the second die over the first die; and disposing the positioning member into the recess. The positioning member includes dielectric, is surrounded by the first bonding layer, and is isolated from the first interconnect structure and the second interconnect structure.

A power inverter module includes a base module having a plurality of electrically conductive layers, including a first conductive layer, a second conductive layer and a third conductive layer. A first terminal is operatively connected to the first conductive layer at a first end and a second terminal is operatively connected to the second conductive layer at the first end. An isolation sheet is sandwiched between the first and second terminals. The first terminal and the second terminal include a respective proximal portion composed of a first material and a respective distal portion composed of a second material. At least one of the first terminal and the second terminal is bent to create an overlap zone such that a gap between the first terminal and the second terminal in the overlap zone is less than a threshold distance. The power inverter module is configured to reduce parasitic inductance.

A method of manufacturing an electronic device comprising the steps of: preparing a substrate comprising an electrically conductive layer; applying a conductive paste on the electrically conductive layer; mounting an electrical component on the applied conductive paste; heating the conductive paste to bond the electrically conductive layer and the electrical component, wherein the conductive paste comprises 100 parts by weight of the metal powder, 5 to 20 parts by weight of a solvent, and 0.05 to 3 parts by weight of a polymer, wherein the polymer comprises a first polymer and a second polymer, wherein the molecular weight (Mw) of the first polymer is 5,000 to 95,000, and the molecular weight (Mw) of the second polymer is 100,000 to 300,000.