Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

The present disclosure relates to a method of interconnecting semiconductor devices and an assembly of interconnected semiconductor devices. The method comprises forming a metal layer on a first connection surface of the first semiconductor device, and forming an oxidant layer on a second connection surface of the second semiconductor device, the first connection surface including first coupling pads, the second connection surface including the second coupling pads. The method further comprises aligning the first connecting pads and respective ones of the second connecting pads to each other, pressing together the metal layer and the oxidant layer, and reacting the metal layer with the oxidant layer under target condition to form a bonding layer. The bonding layer first regions, second regions, and third regions that are conductive regions, and a fourth region that is a nonconductive adhesive region. The method of interconnecting semiconductor devices allows alignment errors, improves yield, and reduces cost.

An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element.

A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.

There is a provided a copper-ceramic bonded body in which a copper member formed of copper or a copper alloy and a ceramic member formed of nitride ceramic are bonded to each other, in which an active element oxide layer containing an active element and oxygen is formed at bonding interfaces between the copper member and the ceramic member, and a thickness t of the active element oxide layer is in a range of 5 nm to 220 nm.

A connection structure including: a first circuit member having a plurality of first electrodes; a second circuit member having a plurality of second electrodes; and an intermediate layer having a plurality of bonding portions electrically connecting the first electrodes and the second electrodes, in which at least one of the first electrode and the second electrode that are connected by the bonding portion is a gold electrode, and 90% or more of the plurality of bonding portions include a first region containing a tin-gold alloy and connecting the first electrode and the second electrode and a second region containing bismuth and being in contact with the first region.

An example device in accordance with an aspect of the present disclosure includes a first layer and a second layer to be bonded to the first layer. The first and second layers are materials that generate gas byproducts when bonded, and the first and/or second layers is/are compatible with photonic device operation based on a separation distance. At least one bonding interface layer is to establish the separation distance for photonic device operation, and is to prevent gas trapping and to facilitate bonding between the first layer and the second layer.

Providing the conductive paste for the material forming the conductive connecting member without disproportionately located holes (gaps), coarse voids, and cracks, which improves thermal cycle and is excellent in crack resistance and bonding strength. An conductive paste including metal fine particles (P) comprising metal fine particles (P1) of one or more than two kinds selected from metal and alloy thereof, having mean primary particle diameter from 1 to 150 nm, and metal fine particles (P2) of same metal as the metal fine particles (P1), having mean primary particle diameter from 1 to 10 m, mixing ratio of (P1/P2) being from 80 to 95 mass % for P1 and from 20 to 5 mass % for P2 (a total of mass % being 100 mass %); and organic dispersion medium (D) comprising organic solvent (S), or organic solvent (S) and organic binder (B), mixing ratio (P/D) of the metal fine particles (P) and the organic dispersion medium (D) being from 50 to 85 mass % for P and from 50 to 15 mass % for D (a total of mass % being 100 mass %).

A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles. The method further includes disposing the semiconductor on the substrate and forming a bonding layer by heating the silver paste, wherein the semiconductor and the substrate are bonded to each other by the bonding layer.