A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.

A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

In a general aspect, an apparatus can include a semiconductor die, a substrate, and a leadframe coupled to the substrate. The apparatus can include a conductive clip coupled to the semiconductor die. The leadframe can be disposed between the semiconductor die and the substrate, and the semiconductor die can be disposed between the conductive clip and the leadframe.

The invention relates to a semiconductor module (1) comprising at least two semiconductor components (10, 20) which are arranged within a housing in each case between two electrical conduction elements (12, 14, 22, 24) and are electrically conductively connected to the electrical conduction elements (12, 14, 22, 24). In this case, the electrical conduction elements (12, 14, 22, 24) respectively have a contact extension (12.1, 14.2, 22.1, 24.1) that is led out of the housing, wherein two contact extensions (12.1, 24.1) arranged in different planes are connected to one another outside the housing via a contact element (5), which forms a current path between the two contact extensions (12.1, 24.1) outside the housing.

Power module includes: first transistors Q1, Q4 forming at least one half bridge, and disposed at upper and lower arms thereof; second transistors QM1, QM4 of which drains are respectively connected to gates G1 and G4 sides of the first transistors, and sources are respectively connected to the sources S1, S4 sides thereof; source signal wiring patterns SSP1, SSP4 respectively connected to the sources S1, S4 of the first transistors; first connected conductors MSW1, MSW4 for respectively connecting between the source signal wiring patterns and the sources of the second transistors; second gate signal wiring patterns MGP1, MGP4 respectively connected to gates MG1, MG4 of the second transistors; and second connected conductors MGW1, MGW4 for respectively connecting between the gate signal wiring patterns and the gates of the second transistors. Lengths of the first connection conductors are respectively equal to or shorter than lengths of the second connection conductors.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

The disclosure relates to a lead frame assembly for a semiconductor device, the lead frame assembly including: a die attach structure and clip frame structure. The clip frame structure includes: a die connection portion configured to contact to one or more contact terminals on a top side of the semiconductor die; one or more electrical leads extending from the die connection portion at a first end, and a lead supporting member extending from a second end of the one or more leads; and a plurality of clip support members arranged orthogonally to the one or more electrical leads. The plurality of support members and the lead supporting member are configured to contact the die attach structure. The present disclosure also relates a die attach structure and clip frame structure for a semiconductor device, a semiconductor device including the same and a method of manufacturing the semiconductor device.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.