A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, the adhesive layer has a first portion that is located between the second and third surface and a second portion that is made of a same material as the first portion and that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.

A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other.

A power module according implementations of the present disclosure includes a bonding layer for bonding two adjacent members. The bonding layer is formed by melting, applying, and solidifying a bonding material that has excellent thermal conductivity and electrical conductivity. The melted bonding material includes a plurality of anti-tilting members. The two members bonded during the process of solidifying the melted bonding material are supported by the plurality of anti-tilting members. This may allow tilting caused during the formation of the bonding layer to be suppressed.

A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.

A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components, and related material films, articles and assemblies.

A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.