Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

A method of manufacturing a component carrier includes: i) forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, with at least one cavity formed in the stack, ii) forming a cluster by encapsulating a first electronic component and a second electronic component in a common encapsulant, and thereafter iii) placing the cluster in the common encapsulant at least partially into the cavity and v) embedding the cluster in the cavity.

An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.

A fan-out packaging method employing a combined process includes: manufacturing at least two layers of basic circuit patterns on a substrate; manufacturing a galvanic isolation layer on one of the two layers of basic circuit patterns; manufacturing a fine circuit pattern on the galvanic isolation layer; using a bonding layer to bond an electronic component to the galvanic isolation layer, and using a patch material to establish an electrical connection between the electronic component and the fine circuit pattern; and using a packaging layer to package the electronic component, wherein the fine circuit pattern has a width less than widths of the basic circuit patterns. In the present disclosure, multiple layers of circuits are manufactured before installation and packaging of electronic components, thereby reducing the number of times an insulation material is to be heated, and broadening the range of available types of insulation materials.

Provided is a semiconductor device manufacturing method through which semiconductor elements are multilayered through the lamination of wafers in which the semiconductor elements are fabricated, the method thereof being suited for efficiently manufacturing semiconductor devices while realizing a large number of wafer lamination. With the method of the present invention, at least two wafer laminates are formed, each wafer laminate having a laminated structure, the structure including a plurality of wafers including an element forming surface and a back surface, with the element forming surface and the back surface facing between adjacent wafers; a through electrode is formed in each wafer laminate with the through electrode extending through an inside of the wafer laminate, from an element forming surface side of a first wafer located at one end of the wafer laminate in a lamination direction, to a position exceeding an element forming surface of a second wafer located at another end; the through electrode is exposed at a back surface side of the second wafer by grinding the back surface side thereof; and two wafer laminates that have been subjected to this exposing step are laminated and bonded while electrically connecting the through electrodes between the wafer laminates.

An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.

A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.