Integrated circuit packaging structure and method

Abstract

An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.

Claims

1. An integrated circuit packaging method, comprising: making a substrate provided with a circuit layer, providing an insulation patch on the substrate, forming fine wirings on the insulation patch, providing at least two of the chips on the substrate, wherein each chip is provided with fine pin(s) and chip pin(s), electrically connecting the chip(s) pin with the circuit layer, electrically connecting the fine pin(s) with the respective fine wiring such that the at least two chips are directly connected by means of the fine wirings, wherein a connection medium is provided between the chips and the fine wirings, the connection medium includes an insulating medium and at least one fine conductive particle distributed within the insulating medium, a spacing between each chip pin and the respective fine pin is less than or equal to a height of the fine conductive particle(s), one end of each fine conductive particle is electrically connected to the respective fine pin, the other end of the fine conductive particle is electrically connected to the respective fine wiring, a spacing between each chip pin and the respective fine wiring is greater than the height of the fine conductive particles, and the chip pin(s) and the fine wiring are not electrically connected by the conductive particle(s).

2. The integrated circuit packaging method according to claim 1, comprising: making the circuit layer provided with circuit pins and the substrate provided with connection through holes, connecting the connection through holes with the circuit pins respectively, placing chips on a top surface of the substrate, connecting the chip pin(s) of each chip with a first opening of the respective connection through hole, forming a conductive layer in the connection through hole by means of the second opening of the connection through hole, such that the conductive layer electrically connects the chip pin(s) with the respective circuit pins; or making the circuit layer provided with circuit pins, placing chips on the top surface of the substrate with the chip pin(s) of each chip facing the substrate, forming connection through holes on the substrate, connecting the connection through holes with the circuit pins respectively, connecting the first opening of each connection through hole with the respective chip pin, forming a conductive layer in the connection through hole by means of the second opening of the connection through hole, such that the conductive layer electrically connects the chip pin(s) to the respective circuit pin.

3. The integrated circuit packaging method according to claim 1, comprising: providing an additional circuit layer on a bottom surface of the substrate and/or inside the substrate, wherein the additional circuit layer is provided with additional pins, and the substrate is provided with additional through holes, connecting the additional through holes with the additional pins respectively, placing the chips on the top surface of the substrate, connecting the chip pin(s) of each chip with the first opening of the respective additional through hole, and forming an additional conductive layer in the additional through hole by means of the second opening of the additional through hole, such that the additional conductive layer electrically connects the chip pin(s) to the respective additional pin; or providing the additional circuit layer with additional pins, placing the chips on the top surface of the substrate, with the chip pin(s) of each chip facing the substrate, forming additional through holes on the substrate, connecting the additional through holes with the additional pins respectively, connecting the first opening of each additional through hole with the respective chip pin, and forming a conductive layer in the additional through hole by means of the second opening of the additional through hole such that the conductive layer electrically connects the chip pin with the respective circuit pin.

4. The integrated circuit packaging method according to claim 1, further comprising: providing an encapsulation layer on the substrate, wherein the chips, the insulation patch, and the fine pins are located between the encapsulation layer and the substrate, and the chips, the insulation patch, and the fine pins are encapsulated and packaged by the encapsulation layer.

5. The integrated circuit packaging method according to claim 1, wherein a conductor layer is provided on the substrate, the insulation patch is provided on the conductor layer, a conductor film is provided on the insulation patch, a thickness of the conductor layer is greater than a thickness of the conductor film, resist(s) is provided on the conductor layer and the conductor film, the resist(s) is provided with a wiring pattern, the conductor layer is etched into the circuit layer by a chemical etching method in accordance with the wiring pattern, and the conductor film is etched into the fine wirings.

6. The integrated circuit packaging method according to claim 1, wherein the circuit layer is provided with on the substrate, the insulation patch is provided on the circuit layer, a photoresist is provided on the insulation patch, wiring grooves are formed in the photoresist, a conductor film is formed in the wiring grooves and on the surface of the photoresist by crystal growth, and the photoresist is removed to form the fine wirings in the wiring grooves.

7. The integrated circuit packaging method according to claim 1, wherein the insulation patch is formed on a carrier, the fine wirings are formed on the insulation patch, the insulation patch along with the fine wirings are transferred to the substrate, and the fine wirings are fixed to the substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a first schematic diagram of an integrated circuit packaging structure and method according to an embodiment of the present disclosure;

(2) FIG. 2 is a second schematic diagram of an integrated circuit packaging structure and method according to an embodiment of the present disclosure;

(3) FIG. 3 is a third schematic diagram of an integrated circuit packaging structure and method according to an embodiment of the present disclosure;

(4) FIG. 4 is a fourth schematic diagram of an integrated circuit packaging structure and method according to an embodiment of the present disclosure;

(5) FIG. 5 is a fifth schematic diagram of an integrated circuit packaging structure and method according to an embodiment of the present disclosure;

(6) FIG. 6 is a first schematic diagram of an integrated circuit packaging structure according to an embodiment of the present disclosure;

(7) FIG. 7 is a second schematic diagram of an integrated circuit packaging structure according to an embodiment of the present disclosure.

REFERENCE SIGNS

(8) 100—substrate, 101—conductor layer, 102—additional conductor layer, 110—circuit layer, 120—additional circuit layer, 130—connection through hole, 140—external port, 200—insulation patch, 201—conductor film, 210—fine wirings, 300—resist, 400—chip, 410—chip pin, 420—fine pin, 500—conductive layer, 610—fine conductive particle, 620—insulating medium.

DETAILED DESCRIPTION OF EMBODIMENTS

(9) The present disclosure will be further described in detail below, but embodiments of the disclosure are not limited thereto.

Embodiment 1

(10) As shown in FIG. 5, and referring to FIG. 1 to FIG. 4, the integrated circuit packaging structure includes: a substrate 100 provided with a circuit layer 110 and a fine wirings 210; chips 400 each provided with fine pin(s) 420 and chip pin(s) 410, wherein the substrate 100 is provided with at least two chips 400. The chip pin(s) 410 of at least one chip 400 is electrically connected to the circuit layer 110. The circuit layer 110 is provided thereon with an insulation patch 200, and the insulation patch 200 is provided thereon with fine wirings 210. The fine pin(s) 420 of the chip 400 is electrically connected to the respective fine wiring 210, and at least two chips 400 are directly electrically connected by means of the fine wirings 210. The chips 400 are electrically connected to the circuit layer 110. The chips 400 can communicate or exchange energy with other electronic devices connected on the circuit layer 110. The chips 400 are directly connected with each other by means of the fine wirings 210, and are not interfered by the circuit layer 110 and not interfered by other electronic devices connected on the circuit layer 110, and the fine wirings 210 are tiny, thus more data transmission channels can be obtained between the chips 400, resulting in a fast transmission speed and wide bandwidth. The insulation patch 200 insulates the fine wirings 210 from the circuit layer 110 to prevent the circuit layer 110 from interfering with the fine wirings 210. For communications between the two chips 400 requiring high speed and wide bandwidth, by using the fine wirings 210, the transmission performance between the chips 400 is improved, and for communications between the two chips 400 which do not require high speed or wide bandwidth, communication can be achieved by means of the circuit layer 110 to reduce the manufacturing cost. On the other hand, by providing the insulation patch 200, each circuit layer 110 can be simultaneously formed, and the insulation patch 200 and the fine wirings 210 may be simultaneously provided at predetermined positions, thus batch flow can be performed to reduce the production cost.

(11) As shown in FIG. 5, each fine pin 420 is provided near an edge of the respective chip 400, and the insulation patch 200 and the fine wirings 210 are provided across the two chips 400. The area occupied by the insulation patch 200 is smaller than the area occupied by the circuit layer 110. The insulation patch 200 and the fine wirings 210 thereon constitute a fine wiring area, and one or two or more fine wiring areas may be provided with between the two chips 400 as needed, or one chip 400 may be electrically connected to two or more chips 400 at the same time by means of two or more fine wiring areas; and providing the fine wiring areas does not need to modify the original circuit layer 110, and the fine wiring areas are flexibly used and may be provided as needed to reduce the cost. The area occupied by the insulation patch 200 may refer to the area occupied by the insulation patch 200 on the substrate 100 and the area occupied by the circuit layer 110 on the substrate 100 when viewed from above in a top view.

(12) The width of the fine wirings 210 refers to the side length of the cross section of the fine wirings 210 on the insulation patch 200. The width of the fine wirings 210 is smaller than the width of the wirings of the circuit layer 110, and the smaller the width of the fine wirings 210, the more connection points that can be obtained in the same space, which is conducive to improvement of the data transmission speed and bandwidth. In this embodiment, the width of the fine wirings 210 is from 0.1 micrometer to 2 micrometers, or from 1 micrometer to 5 micrometers, and may be selected as needed. Preferably, the width of the fine wirings 210 may be selected to be 0.1 μm, 0.2 μm, 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 micrometers, or 5 micrometers.

(13) As shown in FIG. 5, a connection medium is provided with between each chip pin 410 and the respective fine pin 420. The connection medium includes an insulating medium 620 and at least one fine conductive path distributed in the insulating medium 620. The insulating medium 620 separates the respective chip 400 from the fine pin 420 in an insulating way to avoid interference, and the fine pins 420 are electrically connected with each other by means of the fine conductive paths. The form of each fine conductive path includes, but is not limited to, providing conductive particles or solder bumps in the insulating medium 620 to form a fine conductive path; the insulating medium 620 is provided with a fine conductive hole, and a conductive material layer is provided on an inner wall of the fine conductive hole to form a fine conductive path, for example, a through silicon via; conductive bumps are provided with on the fine pins 420 and/or the fine wirings 210, and the conductive bumps constitute a fine conductive path.

(14) The integrated circuit packaging structure further includes an encapsulation layer, the encapsulation layer is not shown in the figures, wherein the chip 400, the fine wirings 210, and the insulation patch 200 are located between the encapsulation layer and the substrate 100, and the chips 400 and the insulation patch 200 on the substrate 100 is packaged by the encapsulation layer. The encapsulation layer can protect the chips 400, the insulation patch 200, and the fine wirings 210 from damage, reduce the influence and interference from external environmental factors on the performance of the chips to ensure the performance of the chips 400.

(15) A heat sink is provided with on each chip 400. The use of the insulation patch may increase the difficulty of heat dissipation toward the substrate of the chip 400, the thermal impedance increases, as fine wirings of high speed and wide bandwidth are used for the communication between the chips 400, and the chip 400 has a high computing speed and heat generation as well, adding the heat sink to the chip 400 (on the side facing away from the substrate) facilitates the heat dissipation of the chip 400 from the heat sink on the back surface, with the heat dissipation not only relying on the heat dissipation channel from the substrate 100, so that the chip 400 can work normally at a higher computing speed. This structural design improves the data communication bandwidth and speed between the chips 400 on the one hand, and ensures that the chip 400 can work normally at a higher computing speed on the one hand, thereby greatly improving the overall computing performance of the system. The heat sink is also packaged on the substrate 100 by the encapsulation layer, and a top surface of the heat sink may be exposed out of the encapsulation layer to dissipate heat or may not be exposed.

(16) As shown in FIG. 7, the substrate 100 is provided with connection through holes 130, wherein the connection through holes 130 are connected with the circuit pins, and a first opening of each connection through hole 130 is connected with the respective chip pin 410, and a second opening of the connection through hole 130 is an operation window, a conductive layer 500 is provided with in the connection through hole 130, and the conductive layer 500 electrically connects the chip pin 410 and the respective circuit pin. The circuit layer 110 is provided with circuits pin, and the circuit layer 110 may be formed on the substrate 100 in advance. Optionally, the circuit layer 110 may be formed on the substrate 100 when the integrated circuit is packaged. The circuit pins may be connection portions directly led out from the circuit layer 110, and may also be extension pins electrically connected to the connection portions, as long as electrically connection with the circuit layer 110 can be achieved by means of the circuit pins. The chips 400 are placed on the substrate 100, and the chips 400 may be fixed to the substrate 100 or may not be fixed. The chips 400 are provided opposite to the substrate 100, and the chips 400 are each provided with chip pin(s) 410 facing the substrate 100, wherein the chip pin(s) 410 of each chip 400 includes, but is not limited to, a connection portion led out from inside the chip 400 or an extension pin electrically connected to the connection portion, as long as electrical connection with the chip 400 can be achieved by means of the chip pins 410. Connection through holes 130 are formed on the substrate 100, each chip pin 410 is connected with the first opening of the respective connection through hole 130, and a conductive layer 500 is formed in the connection through hole 130 by means of the second opening of the connection through hole 130, wherein the conductive layer 500 electrically connects the chip pin 410 to the respective circuit pin; the chip pin(s) 410 is located on the top surface of the substrate 100, the chip 400 and the circuit layer 110 can be electrically connected from the bottom surface of the substrate 100 by means of the second opening of the connection through hole 130 to prevent the chip 400 from blocking the chip pin 410; wherein the connection through hole 130 is connected with the chip pin 410, and the circuit pin is at least partially located near the first opening of the connection through hole 130 or extends deep into the connection through hole 130, so that the conductive layer 500 can be electrically connected to the chip pin 410; the circuit pin is connected to the connection through hole 130, and the circuit pin is at least partially located near the first opening of the connection through hole 130, or near the second opening, or near the inner wall of the connection through hole 130, such that the conductive layer 500 can be electrically coupled to respective circuit pin; the chips 400 may be chips 400 or electronic devices (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas). The chips 400 may be fixed to the substrate 100 by the connection through holes 130 and the conductive layer 500. Optionally, the chips 400 may be fixed to the substrate 100 by other means (including, but not limited to, bonding, molding plastic packaging). In this way, the cost of packaging the integrated circuit can be reduced, and the packaging time can be saved. Further, the plurality of chips 400 can be simultaneously mounted on a large substrate of a very large area, and the batch processing on the large substrate further reduces the cost and saves the packaging time. Moreover, the overall thickness of the substrate 100 and the chip 400 is reduced, and even no gap is required to be reserved between the substrate 100 and the chips 400 (in principle, no gap is required to be reserved, but other materials may be provided with between the substrate 100 and the chip 400 as needed); the connection through holes 130 may be formed using a process that does not require heat welding, thereby avoiding damage to the mechanism and performance of the ultra-thin chips and flexible circuit boards caused by various thermo-mechanical stress distributions during high-temperature thermal cycling. This is very helpful for packaging processes using ultra-thin, flexible circuit boards. On the other hand, in the conventional package technology of wire bonding, wires are used to realize the electrical connection between the chips 400 and the circuit on the substrate 100, and the wires are to be avoided from each other, so that the space to be occupied is relatively large, and in the present disclosure, electrical connection between the chips and the additional circuit layers 120 is realized by forming the connecting the through holes 130 on the substrate 100, the conductive layers 500 is provided within the respective connection through hole 130 without occupying extra space, which can reduce the overall volume after the package, in particular, for ultra-thin circuit boards, their characteristics of being thin and light can be well maintained, for the flexible circuit boards, their flexibility can be well maintained.

(17) Preferably, the method includes but is not limited to the following two methods:

(18) (1) The circuit layer 110 is provided with circuit pins, the substrate 100 is provided with connection through holes 130, wherein the connection through holes 130 are connected with the circuit pins respectively; the chips 400 are placed on the top surface of the substrate 100, the chip pin(s) 410 of each chip 400 is connected with the first opening of the respective connection through hole 130; a conductive layer 500 in the connection through hole 130 by means of the second opening of the connection through hole 130, so that the conductive layer 500 electrically connects the chip pin 410 to the respective circuit pin; or

(19) (2), the circuit layer 110 is provided with circuit pins, the chips 400 are placed on the top surface of the substrate 100, the chip pin(s) 410 of each chip 400 is oriented toward the substrate 100, and the connection through holes 130 are formed on the substrate 100, the connection thorough holes 130 are connected with the circuit pins respectively, and the first opening of each connection through hole 130 is connected with the respective chip pin 410, the conductive layer 500 is formed in the connection through hole 130 by means of the second opening of the connection through hole 130, so that the conductive layer 500 electrically connects the chip pin 410 to the respective circuit pin.

(20) In this embodiment, as shown in FIG. 7, the connection through holes 130 are also additional through holes and an additional circuit layer 120 is respectively provided on the bottom surface of the substrate 100 and inside the substrate 100, wherein the additional circuit layers 120 are each provided with additional pins, and the additional through holes (connection through hole 130) are connected with the additional pins respectively, and the first opening of each additional through hole (connection through hole 130) is connected with the respective chip pin 410, and the second opening of the additional through hole (connection through hole 130) is an operation window, and an additional conductive layer 500 is provided within the connection through hole (connection through hole 130), and the additional conductive layer 500 electrically connects the chip pin 410 and the respective additional pin. Moreover, an external port 140 is provided on the bottom surface of the substrate 100, wherein the external port 140 is electrically connected to at least one of the conductive layers 500. The external port 140 may be connected to other electronic devices to expand the function of the entire integrated circuit, and may also be used to be connected with a power supply, and the chip 400 are directly supplied by the power supply.

(21) The substrate 100 may be a normal circuit board or a flexible circuit board, or the substrate 100 may include at least two layers of flexible circuit boards arranged in a stacked manner. The use of a multiple layers of circuit boards and the multiple layers of circuits therein can provide more possibilities of wiring and improve the using performance of the chip 400; the use of flexible and thin circuit boards reduces the overall weight, volume and thickness of the system. With proper system design and selection of encapsulation layer material, the system as a whole can still possess sufficient flexibility after package and integration and is applicable to wearable products. Moreover, by using the insulation patch 200, the thickness of the fine wirings 210 per se is very small, as long as the insulation patch 200 can satisfy the insulation between the fine wirings 210 and other regions of the substrate 100, and does not require a very large thickness, which facilitate the system as a whole to maintain its flexibility and thinness. The thickness of the fine wirings 210 refers to the side length of the cross section of the fine wirings 210 which is perpendicular to the insulation patch 200, and the thickness of the insulation patch 200 refers to the side length of the cross section of the insulation patch 200 which is perpendicular to the substrate 100. The thickness of the fine wirings 210 refers to the side length of the cross section of the fine wirings 210 which is perpendicular to the insulation patch 200, and the thickness of the insulation patch 200 refers to the side length of the cross section of the insulation patch 200 which is perpendicular to the substrate 100.

(22) In this embodiment, the integrated circuit packaging method mainly includes: prearranging the circuit layer 110 on the substrate 100, prearranging the insulation patch 200 on the substrate 100, forming the fine wirings 210 on the insulation patch 200, providing at least two chips 400 on the substrate 100, wherein each chip 400 is provided with fine pin(s) 420 and chip pin(s) 410, the chip pin(s) 410 is electrically connected to the circuit layer 110, and the fine pin(s) 420 is electrically connected to the respective fine wiring 210, so that the at least two chips 400 are directly connected by means of the fine wirings 210.

(23) When the connection is implemented by means of the connection through holes 130, the method further includes steps of: prearranged circuit pins on the circuit layer 110, prearranging connection through holes on the substrate 100 with 130, connecting the connection through holes 130 with the circuit pins respectively; placing the chips 400 on the top surface of the substrate 100, connecting the chip pin(s) 410 of each chip 400 to the first opening of the respective connection through hole 130; and forming the conductive layer 500 in the connection through holes 130 by means of the second opening of the connection through hole 130, so that the conductive layer 500 electrically connect the chip pin 410 to the respective circuit pin; or providing the circuit layer 110 is with circuit pins, placing the chips 400 on the top surface of the substrate 100 such that the chip pin(s) 410 of each chip 400 faces the substrate 100, forming the connection through holes 130 on the substrate 100, connecting the connection through holes 130 with the circuit pins respectively, connecting the first opening of each connection through hole 130 with the respective chip pin 410, and forming the conductive layer 500 in the connection through hole 130 by means of the second opening of the connection through hole 130 so that the conductive layer 500 electrically connects the chip pin 410 to the respective circuit pin.

(24) When the connection is implemented by means of additional through hole holes, the method further includes steps of: prearranging an additional circuit layer 120 on the bottom surface of the substrate 100 and/or inside the substrate 100, wherein additional pins are prearranged on the additional circuit layer 120, and the substrate 100 is provided with additional thorough holes, wherein the additional through holes are connected with the additional pins respectively; placing the chips 400 on the top surface of the substrate 100, connecting the chip pin(s) 410 of each chip 400 with the first opening of the respective additional through hole; forming an additional conductive layer 500 in the additional through hole by means of the second opening of the additional through hole, so that the additional conductive layer 500 electrically connects the chip pin 410 to the respective additional pin; or prearranging additional pins on the additional circuit layer 120, placing the chips 400 on the top surface of the substrate 100, with the chip pin(s) 410 of each chip 400 oriented toward the substrate 100, forming the additional through holes on the substrate 100, connecting the additional through holes with the additional pins respectively, connecting the first openings of each additional through hole with the respective chip pin 410, and forming the conductive layer 500 in the additional through hole by means of the second opening of the additional through hole, so that the conductive layer 500 electrically connects the chip pin 410 to the respective circuit pin.

(25) The integrated circuit packaging method further includes packaging the chips 400: providing an encapsulation layer on the substrate 100, wherein the chips 400, the insulation patch 200, and the fine wirings 210 are located between the encapsulation layer and the substrate 100, and the encapsulation layer packages the chips 400, the insulation patch 200, and the fine wirings 210. After the package, the whole system composed of the substrate 100, the chips 400, the encapsulation layer, the insulation patch 200, the fine wirings 210, and the like is cut into a plurality of small system units according to preset parameters such as functions, sizes, so that the chips 400 are mounted and packaged on the substrate 100 simultaneously, and then cut into system units of suitable sizes, which can greatly improve production efficiency and reduce cost.

Embodiment 2

(26) The difference between Embodiment 2 and Embodiment 1 is:

(27) As shown in FIG. 1 to FIG. 5, the circuit layer 110 is not prearranged on the substrate 100, and the circuit layer 110 is formed when the fine wirings 210 are formed, the specific manufacturing method is as follows: providing a conductor layer 101 and an additional conductor layer 102 on the substrate 100, providing an insulation patch 200 on the conductor layer 101, and providing a conductor film 201 on the insulation patch 200, wherein a thickness of the conductor layer 101 is much larger than a thickness of the conductor film 201, and a resist 300 is provided on the conductor layer 101, the additional conductor layer 102, and the conductor film 201, a wiring pattern is provided with in the resist 300, the conductor layer 101 is etched into the circuit layer 110 by chemical etching according to the wiring pattern, and the conductor film 201 is etched into the fine wirings 210. After the resist 300 is provided on the conductor layer 101, the additional conductor layer 102, and the conductor film 201, chemical etching may be simultaneously performed, and the circuit layer 110, the additional circuit layer 120, and the fine wirings 210 are simultaneously formed in accordance with the wiring pattern, thereby the steps are saved, the efficiency is improved, and the production cost is reduced. All the circuit layers 110, additional conductor layers 102, and conductor films 201 on multiple substrates 100 may be simultaneously processed, which is advantageous for mass production and further reduces the cost. Further, the thickness of the conductor film 201 is equivalent to the thickness of the fine wirings 210, and the thickness of the conductor layer 101 is equivalent to the thickness of the circuit layer 110, for example, when the thickness of the fine wirings 210 is much smaller than the thickness of the circuit layer 110, the thickness of the conductor film 201 needs to be much smaller than the thickness of the conductor layer 101.

Embodiment 3

(28) The difference between Embodiment 3 and Embodiment 1 is:

(29) The insulation patch 200 and the fine wirings 210 are formed by: prearranging a circuit layer 110 on the substrate 100, providing an insulation patch 200 on the circuit layer 110, and providing a photoresist on the insulation patch 200, wherein wiring grooves are formed in the wiring grooves and conductor films are grown in the wiring grooves and on the surface of the photoresist, thereby the fine wirings 210 are formed in the wiring groove after the photoresist is removed.

Embodiment 4

(30) The difference between Embodiment 4 and Embodiment 1 is:

(31) The insulation patch 200 and the fine wirings 210 are formed by: forming a removable (peelable) layer and an insulation patch 200 on a carrier, forming fine wirings 210 on the insulation patch 200, transferring the insulation patch 200 together with the fine wirings 210 to the substrate 100, and fixing the fine wirings 210 to the substrate 100. For example, the insulation patch 200 and the fine wirings 210 may be flipped onto another carrier, and the other carrier flips the insulation patch 200 and the fine wirings 210 onto the substrate again, so that the fine wirings 210 faces upward, and the fine wirings 210 together with the insulation patch 200 therebelow are fixed to the substrate 100.

Embodiment 5

(32) The difference between Embodiment 5 and Embodiment 1 is:

(33) As shown in FIG. 6, the fine pins 420 are electrically connected with the fine wirings 210 by: providing a connection medium between the chips 400 and the fine pins 420, wherein the connection medium includes an insulating medium 620 and at least one fine conductive particle 610 distributed in the insulating medium 620, the fine conductive particles 610 are insulated from each other by the insulating medium 620, and a spacing between each chip pin 410 and the respective fine pin(s) 420 is less than or equal to the height of the fine conductive particles 610, and the spacing between the fine pin 420 on each chip 400 and the respective fine wiring 210 on the insulation patch 200 is small, thus the fine conductive particles 610 are distributed at a high density, placing the chip 400 on the substrate 100, electrically connecting one end of each fine conductive particle 610 to the respective fine pin 420, and electrically connecting the other end of the fine conductive particle to the fine wiring 210 to form at least one conductive path formed by the fine conductive particles 610; a spacing between the chip pin 410 and the circuit layer 110 is greater than the height of the fine conductive particles 610, and when the spacing between the chip pin 410 and the circuit layer 110 is large, the fine conductive particles 610 are distributed at a low density, thus the chip pin 410 and the circuit layer 110 cannot be electrically connected by means of the conductive particles, and any conductive path formed by the fine conductive particles 610 cannot be formed, thereby electrical isolation between the chip pin 410 and the circuit layer 110 is maintained. The insulating medium 620 is provided between each chip 400 and the respective fine pin 420, and the chip 400 is pushed toward the insulation patch 200 to reach a preset position, since a spacing between the chip pin 410 and the respective fine pin 420 is less than or equal to the height of fine conductive particles 610, the fine conductive particles 610 are squeezed, one end thereof is electrically connected to the fine pin 420, and the other end thereof is electrically connected to the fine respective wiring 210, thereby electrically connecting the fine pin 420 and the fine wiring 210; the spacing between the chip pin 410 and the circuit layers 110 is greater than the height of the fine conductive particles 610, and the fine conductive particles 610 between the chip pin 410 and the circuit layer 110 cannot simultaneously contact the chip pin 410 and the fine wiring 210, so the fine conductive particles 610 cannot electrically connect the chip pin 410 and the fine wiring 210. In this connection manner, the electrical connection between the fine pins 420 and the fine wirings 210 is realized in the process of placing the chips 400 on the insulation patch 200, thus the processes are simple with high efficiency.

(34) The technical features of the above embodiments may be combined at will. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it is considered as fallen with the range described in this specification.

(35) The above embodiments are merely illustrative of several embodiments of the present disclosure, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the present disclosure. It should be noted that various variations and modifications may be made by those ordinarily skilled in the art without departing from the conception of the present disclosure and they shall all be considered as fallen within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the appended claims.