The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.

A semiconductor package includes at least one first semiconductor chip on a substrate. The substrate includes a body layer having top and bottom surfaces, first fiducial marks on the top surface of the body layer, and a first protection layer on at least edges of the first fiducial marks, the first protection layer having first openings that expose top surfaces of the first fiducial marks. The first fiducial marks include first mark exposure portions that are each exposed without being covered by the first protection layer. Each of the first mark exposure portions includes a first circular segment and at least four first protruding segments outwardly protruding from the first circular segment. Angles between sidewalls of adjacent first protruding segments may be identical with each other. Lateral lengths of the first protruding segments that outwardly protrude from the first circular segment may be identical with each other.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

An exemplary embodiment provides a conductive connecting member, and a display device including the same, that includes a flexible elongated body and terminals formed at opposite ends of the body to be electrically connected to the body, wherein the body may include terminal areas in which the terminals are formed and a central area disposed between the terminal areas, and wherein two or more recess portions may be formed in edges of the body within the central area of the body.

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

A package structure includes a first package including a first substrate and a first molded portion disposed on the first substrate; and a rigid-flexible substrate disposed on at least a portion of the first package and having a rigid region and a flexible region. The first molded portion is disposed between the first substrate and the rigid-flexible substrate.

A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.