In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

A method and apparatus capable of adjusting a signal level in a wireless communication system are provided. An electronic device includes an oscillator configured to output a local oscillator (LO) signal, a mixer configured to convert a frequency band of a first signal based on the LO signal and output a third signal, and a feedback circuit configured to output a feedback signal for adjusting a magnitude of the LO signal, wherein the mixer is further configured to adjust a magnitude of LO signal based on the feedback signal.

An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

A control circuit for an electric leakage circuit breaker, capable of preventing an error in determining an electric leakage generation due to an offset voltage of an input amplifier, including, a zero phase current transformer configured to detect a zero phase current on a circuit as a leakage detection signal, a filter circuit section configured to remove a high frequency noise included in the leakage detection signal, an input amplifier configured to a voltage formed by a current of the leakage detection signal and an impedance of the filter circuit section, and includes a pair of transistors, a base current generator commonly connected to the bases of the pair of transistors and configured to supply the same amount of base current to the pair of transistors, and a trip determination circuit section configured to determine whether to output a trip control signal.

In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

Examples of circuits and amplifiers include recirculation circuitry to reduce or cancel error currents produced by target bipolar junction transistors (BJTs). In an example, first recirculation circuitry is coupled to the base of a first signal-conveyance BJT and to one of the collector or the emitter of the first signal-conveyance BJT; second recirculation circuitry is coupled to the base of a second signal-conveyance BJT and to one of the collector or the emitter of the second signal-conveyance BJT; and biasing circuitry is coupled to the first and second recirculation circuitry. The recirculation circuitry may be implemented with BJTs or MOSFETs. Configurations are provided in which error current(s) are recirculated between the base and collector/emitter node of each target BJT.

A baseline restorer circuit including a controller; a sample control circuit arranged to receive an input voltage signal that is output from a circuit stage comprising an amplifier, and configured to capture a sample of the input voltage signal at a sampling time in response to receiving a control signal from the controller; an analogue processing stage to receive the sample and a constant baseline reference voltage and selectively process the sample to provide an output voltage; a transconductance stage to convert the output voltage to a compensation current and supply the compensation current to an input of the circuit stage; and a change detector to monitor if the input voltage signal changes during a time interval around the sampling time, and if no change is detected in the input voltage signal during the time interval, the controller is configured to control the analogue processing stage to process the sample.

A receiver circuit includes: a constant current circuit to generate second paired current signals according to first paired current signals; a current splitter circuit to output third paired current signals generated from the second paired current signals, from a first output node and a second output node; and a differential TIA circuit to output paired voltage signals from a first output terminal and a second output terminal, according to the third paired current signals input from a third input node and a fourth input node. The differential TIA circuit includes a first feedback resistor element connected between the third input node and the second output terminal, and a second feedback resistor element connected between the fourth input node and the first output terminal. Average voltages of the first and second output nodes and the first and second output terminals are set to be equivalent to each other.