Methods and systems are disclosed for decoding codewords, wherein codewords comprise at least one circulant and are stored in a first dimension of a matrix, and wherein each circulant in a codeword is associated with a location in a second dimension in the matrix. The method includes determining whether a first location in a second dimension of a first circulant of a first codeword corresponds to a second location in the second dimension of a second circulant of a second codeword. The method includes, in response to determining that the first location does not correspond to the second location, decoding the first and second circulant with a first decoding process. The method includes, in response to determining that the first location corresponds to the second location, decoding the first and second circulant with a second decoding process.

An error correction method includes performing a first error correction operation, the first error correction operation including performing a syndrome check operation by calculating a syndrome matrix corresponding to a codeword based on a parity check matrix, performing a decoding operation for the codeword according to a result of the syndrome check operation, and iterating the decoding operation until the syndrome check operation is passed for a codeword acquired as the decoding operation is performed or an iteration count of the decoding operation reaches a threshold count; accumulating syndrome matrixes, which are calculated as the decoding operation is iterated, to an accumulation matrix; and performing a second error correction operation for a last codeword acquired through the iterating of the decoding operation for the codeword, based on the accumulation matrix, when the iteration count reaches the threshold count.

Systems, methods, and devices for encoding and decoding data packets for transmission across a data network. To encode, data packets are first subjected to a an outer code process to result in outer coded packets. The outer coded packets are then divided into generations or groups of outer coded packets, each group or generation having an equal number of packets. Output packets are then created by forming random linear combinations of the outer coded packets from a specific generation or group of outer coded packets. The coefficients for the various elements of each linear combination is selected from a Galois field of values. To decode the incoming packets, enough packets are received until an iterative decoding process can be initiated.

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

Disclosed herein is an encoder for encoding digital data, said encoder comprising one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps:—combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word,—encoding the local information word such as to generate a local code word,—outputting a reduced local code word and handing the same reduced local code word over to said interconnect for forwarding said same reduced local code word via said interconnect to another component encoder or to itself, wherein said encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.