Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

An apparatus and method are provided. The apparatus includes a decoder including a first input configured to receive transport blocks, a second input, and an output configured to provide a decoded codeword, and an offset value updater including an input connected to the output of the decoder, and an output, connected to the second input of the decoder, configured to provide an updated offset value.

Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs). For the most part, the provided embodiments can be implemented with nearly all available current encoding/decoding polar code techniques

A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.

A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

A reception unit for use in a data link and a method for error correction on a reception word in a data link are specified. A low-density parity-check code, LDPC code, is used to iteratively adapt the reception word by virtue of bit node messages and check node messages being exchanged. The check node messages that are transmitted to the bit nodes are quantized in three levels and adopt the values −1, 0 or +1. The method may thus be implemented with low computational expenditure.

A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.