Provided is an encoder, a decoder, a computer-readable medium and methods of forward error correction channel encoding/decoding within a HARQ scheme, based on a generalized quasi-cyclic low-density parity-check code comprising a Cordaro-Wagner component code.

A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.

An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.

Provided herein may be an error correction circuit for detecting a trapping set and a method of operating the error correction circuit. The error correction circuit may include a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme, and a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy, wherein the trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations. In response to detecting a stall condition in the plurality of error correction iterations, a maximum stop condition is increased. The maximum stop condition is a maximum iteration count threshold or a maximum decoding time threshold. The maximum stop condition triggers a stopping of the bit flipping decoder if the codeword is not decoded when the maximum stop condition is satisfied.

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations using a first plurality of bit flipping rules. In response to detecting a stall condition in the plurality of error correction iterations, a second plurality of bit flipping rules is selected. In each of one or more subsequent error correction iterations, the bit flipping decoder flips one or more of the plurality of bits in the codeword using the second plurality of bit flipping rules. The second plurality of bit flipping rules differs from the first plurality of bit flipping rules.

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations. In response to detecting a stall condition in the plurality of error correction iterations, a maximum stop condition is increased. The maximum stop condition is a maximum iteration count threshold or a maximum decoding time threshold. The maximum stop condition triggers a stopping of the bit flipping decoder if the codeword is not decoded when the maximum stop condition is satisfied.

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations using a first plurality of bit flipping rules. In response to detecting a stall condition in the plurality of error correction iterations, a second plurality of bit flipping rules is selected. In each of one or more subsequent error correction iterations, the bit flipping decoder flips one or more of the plurality of bits in the codeword using the second plurality of bit flipping rules. The second plurality of bit flipping rules differs from the first plurality of bit flipping rules.

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received from a memory device. One or more of the plurality of bits in the codeword are flipped in each of a plurality of error correction iterations. Each bit is flipped using a first bit flipping criterion that includes comparing a first bit flipping threshold and an energy function of each bit. Responsive to the determining an iteration count threshold is satisfied and a parity violation count threshold is satisfied, one or more of the plurality of bits in the codeword are flipped using a second bit flipping criterion for one or more error correction iterations. The second bit flipping criterion differs from the first bit flipping criterion.