A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

The present disclosure relates to methods and apparatuses for generating a low-density parity-check code basis matrix. One example method includes obtaining a low-density parity-check code mother matrix, and generating a 1.sup.st matrix to a q.sup.th matrix one by one, where q is a preset positive integer. A P.sup.th matrix in the 1.sup.st matrix to the q.sup.th matrix is generated in the following manner: selecting a to-be-replaced matrix element in a (P1).sup.th matrix, where the to-be-replaced matrix element is a matrix element having a value that is not 1 in the (P1).sup.th matrix, determining a P.sup.th shift factor corresponding to the to-be-replaced matrix element, and replacing the to-be-replaced matrix element in the (P1).sup.th matrix with the P.sup.th shift factor to obtain the P.sup.th matrix whose cycle length property is better than a cycle length property of the (P1).sup.th matrix.

A data storage system performs operations including receiving a data write command specifying data to be written; selecting an irregular LDPC encoding scheme of a plurality of available irregular LDPC encoding schemes available to the encoder in accordance with (i) a working mode of the data storage system, (ii) device-specific criteria and/or (iii) a data type of the specified data; and encoding the specified data to be written using the selected irregular LDPC encoding scheme.

A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form ln memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the ln memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.

A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

The present disclosure relates to a communications field, and discloses a method for generating a base matrix of an LDPC code, an encoding/decoding method, and a device, to resolve a problem that a probability of a decoding error increases because performance of a transformed check matrix cannot be ensured due to a poor puncturing pattern. A specific solution is as follows: A size of a check bit part of a base matrix is determined based on a required minimum bit rate, and the check bit part of the base matrix is determined based on the size of the check bit part and an initial matrix. The initial matrix is a matrix with a size of mm that has a bidiagonal structure, the check bit part is a k-order transformation matrix H.sub.k obtained after the initial matrix is transformed k times, k meets 2.sup.k1m<T2.sup.km, and T is the size of the check bit part. An information bit part of the base matrix is determined based on the check bit part, and the base matrix is obtained based on the check bit part and the information bit part. The present disclosure is used in an encoding/decoding process.

A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[H.sub.d|H.sub.p], H.sub.d is the data portion, and H.sub.p is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Disclosed herein are a channel coding/decoding method in which a parity check matrix is transformed and an apparatus using the same. The channel-coding method includes loading a first exponent matrix, transforming the first exponent matrix into a second exponent matrix, creating a parity check matrix corresponding to a required block size using the second exponent matrix, and performing LDPC encoding using the parity check matrix.