Patent classifications
H03M13/118
MEMORY CONTROLLER
A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.
In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
Vertical Layered Finite Alphabet Iterative Decoding
This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.
METHODS AND APPARATUS FOR PROCESSING LDPC CODED DATA
Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.
Apparatus and method for LDPC encoding suitable for highly reliable and low latency communication
Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
METHOD AND DEVICE OF SELECTING BASE GRAPH OF LOW-DENSITY PARITY-CHECK CODE
A method and a device of selecting a base graph of a low-density parity-check code are provided. The method includes: acquiring a data information length and a channel coding rate of to-be-encoded data; determining a target base graph selection strategy according to the data information length and an information length range of a base graph; determining a target base graph for the to-be-encoded data according to the target base graph selection strategy and the channel coding rate.
TRANSMISSION METHOD, TRANSMISSION APPARATUS, RECEPTION METHOD AND RECEPTION APPARATUS
A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.
MEDIA CONTENT-BASED ADAPTIVE METHOD, DEVICE AND SYSTEM FOR FORWARD ERROR CORRECTION (FEC) CODING AND DECODING OF SYSTEMATIC CODE, AND MEDIUM
A media content-based adaptive method, device and system for Forward Error Correction (FEC) coding and decoding of a systematic code, and a medium are provided. The method includes: dividing, according to the importance of media content, source data into N types of source data packets according to priorities; generating N types of intermediate codes according to the N types of source data packets and the priorities thereof; setting, according to the N types of intermediate codes, recovery data of N types of source data according to a channel condition, and generating coded symbols of N types of systematic codes; receiving the coded symbols, and arranging and sorting the coded symbols according to decoding requirements; and decoding, according to the number of received coded symbols, intermediate codewords according to different situations, and recovering the corresponding source data packets according to the intermediate codewords.
Supporting multiple page lengths with unique error correction coding via galois field dimension folding
Disclosed are methods and devices for supporting multiple page lengths with unique error correction coding via Galois field dimension folding. In one embodiment, a method comprises receiving a write instruction, the write instruction including user data; generating extended user data based on the user data, the extended user data including at least one symbol comprising a bit of the user data and a pre-stored bit pattern; generating parity data by encoding the extended user data; generating parity extension data by encoding the bit of the user data; writing a codeword to a page of a non-volatile memory device, the codeword including the parity extension data, the user data, and the parity data.