An ion implanting method includes providing a gas having a bonding energy ranged from about 220 kJ/mol to about 450 kJ/mol; ionizing the gas to form a plurality of types of ions; and directing at least one of the types of the ions to implant a substance. The gas includes at least one of N.sub.2H.sub.4, CH.sub.3N.sub.2H.sub.3, C.sub.6H.sub.5N.sub.2H.sub.3, CFCl.sub.3 and C(CH3).sub.3F.

A process of forming electronic device can include providing a substrate having a first portion and a second portion; introducing a nitrogen-containing species into the second portion of the substrate; and exposing the substrate to an oxidizing ambient, wherein a thicker oxide is grown from the first portion as compared to the second portion. In an embodiment, the process can include removing the first portion while the second portion of the substrate that includes the nitrogen-containing species remains. In another embodiment, the process can be used to form different thicknesses of an oxide layer at different portions along a sidewall of a trench. The process may be used in other applications where different thicknesses of oxide layers are to be formed during the same oxidation cycle, such as forming a tunnel dielectric layer and a gate dielectric layer for a floating gate memory cell.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability.

The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a surface portion 10A of a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions 16, in the surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer, the epitaxial layer 20 having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer 18.

An object is to provide a method of producing a semiconductor epitaxial wafer having higher gettering capability and a reduced haze level of the surface of a semiconductor epitaxial layer.

The method of producing a semiconductor epitaxial wafer, according to the present invention includes: a first step of irradiating a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion 10A of the semiconductor wafer; a second step of performing heat treatment for crystallinity recovery on the semiconductor wafer 10 after the first step such that the haze level of the semiconductor wafer surface portion 10A is 0.20 ppm or less; and a third step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer after the second step.

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate.

This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.