A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.

A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.

A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

A semiconductor device includes a substrate, a gate oxide layer, a gate electrode and an injection region. The substrate includes a trench, a source region, a drain region and a channel region. The trench includes trench sidewalls and a trench bottom wall. The gate oxide layer is disposed in the trench. The gate oxide layer includes a groove. The gate electrode is disposed in the groove. The injection region is located on at least a side of the trench bottom wall, and at least a part of the injection region is closer to the drain region than the source region so that a threshold voltage at a portion of the channel region close to the injection region is less than a threshold voltage at a portion of the channel region far from the injection region.

A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area; forming a first active region in the first circuit area and a second active region on the second circuit area; forming first stacks with a first gate spacing on the first active region and second gate stacks with a second gate spacing on the second active region, the second gate spacing being different from the first gate spacing; performing an ion implantation to introduce a doping species to the first active region; performing an etching process, thereby recessing both first source/drain regions of the first active region with a first etch rate and second source/drain regions of the second active region; and epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. An insulating material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A first insulating layer is formed between the insulating material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region. A conductive layer is formed over the semiconductor layer. The source region is coupled to the conductive layer.

A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.

Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.