The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the substrate; performing a first ion implantation process on the first portion of the substrate to form a body region in the substrate, the body region being doped with first dopant ions and extending to under a remaining portion of the gate material layer; and forming a gate electrode by performing a second etching process on the remaining portion of the gate material layer to remove a second portion of the gate material layer, the second portion of the gate material layer being located on a side away from the body region.

A semiconductor device includes a silicon-on-insulator (SOI) substrate and transistor cells electrically coupled in parallel to form a power transistor. Each transistor cell includes a source region in a silicon layer of the SOI substrate, a body region in the silicon layer and adjoining the source region, a gate structure configured to control a channel within the body region, a drain region in the silicon layer, and a drift region laterally separating the body region from the drain region. Each gate structure includes a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm. An effective length of the channel of each transistor cell is in a range of 50 nm to 500 nm. The power transistor has a maximum rated voltage in a range of 5V to 60V. Corresponding methods of producing the semiconductor device are also described.

A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.

A semiconductor device includes a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is over a semiconductor substrate. The drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. The source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. The drain region is in the drift region. The doped region is in the drift region and between the drain region and the gate structure. From a top view the doped region has a strip pattern extending in parallel with a strip pattern of the gate structure.

A method of making an integrated circuit includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type. The drain well includes a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant. The method further includes forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well being adjacent to the drift region in the substrate. The method includes forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well. The method includes forming a drain low-density doped (LDD) region in the second zone of the drain well.

Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

A method for forming reliefs on the surface of a substrate, including a first implantation of ions in the substrate according to a first direction; a second implantation of ions in the substrate according to a second direction that is different from the first direction; at least one of the first and second implantations is carried out through at least one mask having at least one pattern; an etching of areas of the substrate having received by implantation a dose greater than or equal to a threshold, selectively to the areas of the substrate that have not received via implantation a dose greater than said threshold; the parameters of the first and second implantations being adjusted in such a way that only areas of the substrate that have been implanted both during the first implantation and during the second implantation receive a dose greater than or equal to said threshold.

A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure, etching first mask layer and second mask layer to expose a portion of a first semiconductor fin not covered by the first gate structure, performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion of the first semiconductor fin located below the first gate structure, etching the first semiconductor fin to remove a portion of an exposed portion of the first semiconductor fin, and epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first source region and a first drain region.

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.