A substrate treating apparatus and a substrate treating method are provided. The substrate treating apparatus includes a support member to support a substrate, a treatment liquid nozzle to supply a treatment liquid to the substrate positioned on the support member, and a controller to control the treatment liquid nozzle such that the treatment liquid supplied to the substrate is differently discharged in a low-flow-supply section and a high-flow-supply section in which an average discharge amount per hour is more than an average discharge amount per hour in the low-flow-supply section.

An optical element is provided. The optical element includes a substrate; a plurality of metal grids formed on the substrate; an oxide layer formed on the substrate between the plurality of metal grids; and a plurality of organic layers formed on the plurality of metal grids, wherein the width of the organic layer is greater than the width of the metal grid, and there is at least one gap between the organic layer and the oxide layer.

An etchant composition for etching a triple layer metal wiring structure of molybdenum/copper/molybdenum or molybdenum alloy/copper/molybdenum alloy, and a use thereof are disclosed. The etchant composition includes hydrogen peroxide, glycol, an etching inhibitor, a chelating agent, an etching additive, a pH adjuster, and water, The etchant can not only slow down the decomposition of hydrogen peroxide, but also extend the lifespan of the etchant, thereby greatly reducing the costs of the etchant in the manufacturing process, and improving the safety factor of the etchant.

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

An object of the present invention is to provide a terahertz oscillator that does not have an MIM capacitor structure of which producing is intricacy, and oscillates due to resonance of an RTD and stabilizing resistors. The present invention is a terahertz oscillator, wherein a slot antenna having a slot is formed between a first electrode plate and a second electrode plate which are applied a bias voltage, stabilizing resistors to respectively connect to the first electrode plate and the second electrode plate are provided in the slot, an RTD is provided on the second electrode plate through a mesa, and a conductive material member to form an air bridge between the first electrode plate and the mesa is provided, and wherein an oscillation in a terahertz frequency band is obtained due to a resonance of the RTD and the stabilizing resistors.

In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of Si.sub.xGe.sub.1-x, where 0≤x≤0.3, the first semiconductor layer is made of Si.sub.yGe.sub.1-y, where 0.45≤y≤1.0, and the second semiconductor layer is made of Si.sub.zGe.sub.1-z, where 0≤z≤0.3.

A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n.sup.+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n.sup.+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Provided is a method for processing a substrate having a metal formed on a planned dividing line along the planned dividing line, the method including a processed groove forming step of forming a processed groove in the substrate along the planned dividing line, and a burr removing step of, after the processed groove forming step is performed, making an etchant that includes at least an oxidizing agent and to which an ultrasonic vibration is imparted come into contact with the substrate, suppressing ductility of a metallic burr generated on a periphery of the formed processed groove and increasing fragility of the burr by modifying the burr by the oxidizing agent included in the etchant, and removing the burr by the ultrasonic vibration.

A semiconductor device includes a semiconductor substrate, a pair of source/drain regions on the semiconductor substrate, and a gate structure on the semiconductor substrate and between the pair of source/drain regions. The gate structure includes a first metal layer and a second metal layer in contact with the first metal layer. A sidewall of the first metal layer and a top surface of the semiconductor substrate form a first included angle, a sidewall of the second metal layer and the top surface of the semiconductor substrate form a second included angle. The second included angle is different from the first included angle.