The present invention provides a treatment liquid exhibiting excellent selectivity in dissolving SiGe in a case where the SiGe is etched with the treatment liquid. The present invention also provides a treatment liquid container relating to the treatment liquid.

The treatment liquid according to an embodiment of the present invention contains a fluoride ion source, an oxidant, an acetate solvent, and an additive, in which the additive is an additive that does not contain a Si atom.

A substrate processing apparatus includes a temperature detector and a controller. The temperature detector detects a temperature of processing liquid before the temperature of the processing liquid in pre-dispensing in progress reaches a target temperature. The controller sets discharge stop duration of the processing liquid in the pre-dispensing based on target temperature prediction duration. The target temperature prediction duration is prediction duration until the temperature of the processing liquid reaches the target temperature from a detection temperature. The detection temperature is the temperature of the processing liquid detected by the temperature detector before the temperature of the processing liquid reaches the target temperature. The target temperature prediction duration is determined based on a temperature profile. The temperature profile indicates a record of the temperature of the processing liquid changing over time when the pre-dispensing processing was performed in the past according to the pre-dispensing condition.

A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

A method for manufacturing a semiconductor-on-insulator substrate by BESOI comprising the following steps: a) provide a structure comprising a first substrate, a first stopping layer made of SiGe having an atomic percentage of Ge lower than or equal to 30%, an intermediate layer, a second stopping layer made of SiGe having a thickness smaller than the thickness of the first stopping layer and an atomic percentage of Ge higher than or equal to 20%, optionally an active area formed by a layer made of silicon or by a stack of active layers made of Si and SiGe, a dielectric layer, a second substrate, b) thin and then etch the first substrate made of silicon, from the first main face up to the second main face, c) successively remove the first stopping layer, the intermediate layer, and optionally the second stopping layer to obtain a SOI or SiGeOI substrate.

A method of manufacturing a semiconductor device includes forming a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer, forming a sacrificial cladding layer over at least sidewalls of the exposed hard mask layer and stacked layer, forming layers of a first dielectric layer and an insertion layer over the sacrificial cladding layer and the fin structure, performing an annealing operation to convert a portion of the layers of the first dielectric layer and the insertion layer from an amorphous form to a crystalline form, and removing the remaining amorphous portion of the layers of the first dielectric layer and the insertion layer to form a recess.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method includes: providing a substrate including a core NMOS area, a core PMOS area and a peripheral NMOS area; performing oxidation treatment on the substrate in the core PMOS area to convert a thickness of a part of the substrate in the core PMOS area into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS area; forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and forming a gate on the gate dielectric layer.

The present disclosure relates to a wafer, a manufacturing method thereof, and a semiconductor device. The wafer manufacturing method includes: providing a wafer having a scribe lane for die cutting. A plurality of scribe-lane through-silicon-vias is formed at the scribe lane, and the scribe-lane through-silicon-vias are filled with a protective material to form the scribe lane. Through the technique of forming through-silicon vias at the scribe lane and filling them with protective materials, performing cutting along the line of the scribe-lane through-silicon-vias during wafer scribing, the cutting stress is reduced so and damage to the die area is prevented. The scribe-lane through-silicon-vias can effectively reduce the scribe lane width, which is conducive to miniaturizing the scribe lane and improving the effective utilization of wafers.

The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

[summary]

An epitaxial wafer is disclosed. The epitaxial wafer includes a substrate; and a stack disposed on the substrate, wherein the stack includes silicon (Si) layers and silicon germanium (SiGe) layers alternately stacked on top of each other, wherein the silicon germanium layer is doped with boron (B) or phosphorus (P).