Interpenetrating polymer networks (IPNs) for a forming polishing pad for a semiconductor fabrication operation are disclosed. Techniques for forming the polishing pads are provided. In an exemplary embodiment, a polishing pad includes an interpenetrating polymer network formed from a free-radically polymerized material and a cationically polymerized material.

A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.

Provided are a method and apparatus for final polishing of a silicon wafer. The method for final polishing includes: within a predetermined period of time remaining before completion of the final polishing, forming a hydrophilic silicon oxide film on a surface of the silicon wafer by using both a polishing slurry and an oxidizing solution as a polishing liquid.

A temporary adhesive material for wafer processing temporarily bonds a support to a wafer having a circuit-forming front and back surface for processing, including a composite temporary adhesive material layer having at least a two-layer structure of first and second temporary adhesive layers, the first layer including a thermoplastic resin layer that is releasably adhered to the wafer's front surface; and the second layer including a photo-curing siloxane polymer layer laminated on the first layer. A wafer processing laminate, a temporary adhesive material for wafer processing, and a method for manufacturing a thin wafer using the same, which suppress wafer warpage at the time of heat-bonding, have excellent delaminatability and cleaning removability, allow layer formation with uniform film thickness on a heavily stepped substrate, are highly compatible with steps of forming TSV, etc., have excellent thermal process resistance, and are capable of increasing productivity of thin wafers.

The invention provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) an anionic polymer having a weight average molecular weight of about 400 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 1 cPs, a ratio of viscosity (cPs) to wt. % of silica abrasive of about 0.2 cPs/wt. % to about 1.5 cPs/wt. %, and a pH of about 9 to about 12. The invention additional provides a chemical-mechanical polishing composition comprising: (a) about 3.0 wt. % to about 10 wt. % silica abrasive; (b) a nonionicpolymer having a weight average molecular weight of about 300 kDa to about 7000 kDa; and (c) water, wherein the polishing composition has a viscosity of at least about 2 cPs, and a pH of about 9 to about 12. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising silicon oxide, silicon nitride, polysilicon, or combinations thereof, using said compositions.

The present invention addresses the problem of providing novel techniques for manufacturing a SiC substrate that enables reduced material loss when a strained layer is removed. The present invention is a method for manufacturing a SiC substrate 30 which includes a strained layer thinning step S1 for thinning a strained layer 12 of a SiC substrate body 10 by moving the strained layer 12 to a surface side. Including such a strained layer thinning step S1 in which the strain layer is moved to (concentrated toward) the surface side makes it possible to reduce material loss L when removing the strained layer 12.

A polishing composition according to the present invention contains zirconia particles, a selectivity improver for improving a ratio of a polishing speed for an organic material (b) to a polishing speed for a material (a) having a metal-nitrogen bond, and a dispersing medium, wherein in a particle size distribution of the zirconia particles obtained by a laser diffraction/scattering method, a diameter (D50) of the particles when a cumulative volume of the particles from a fine particle side reaches 50% of a total volume of the particles is 5 nm or more and 150 nm or less, and a pH of the polishing composition is less than 7.

Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic metal oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates. Chemical additives comprise at least one nitrogen-containing aromatic heterocyclic compound and at least one non-ionic organic molecule having more than one hydroxyl functional group organic.

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.