A method for fabricating a radio-frequency device involves providing a substrate structure including a silicon handle wafer, an oxide layer formed on the silicon handle wafer, and an active silicon layer disposed on the oxide layer. The method further involves patterning and etching the active silicon layer and the oxide layer to form a frontside opening in the active silicon layer and the oxide layer exposing a top surface of the silicon handle wafer and converting the exposed top surface of the silicon handle wafer to porous silicon

A method for fabricating a radio-frequency device involves providing a substrate structure including a silicon handle wafer, an oxide layer formed on the silicon handle wafer, and an active silicon layer disposed on the oxide layer. The method further involves patterning and etching the active silicon layer and the oxide layer to form a frontside opening in the active silicon layer and the oxide layer exposing a top surface of the silicon handle wafer and converting the exposed top surface of the silicon handle wafer to porous silicon

A method for forming a thermoelectric element for use in a thermoelectric device comprises forming a mask adjacent to a substrate. The mask can include three-dimensional structures phase-separated in a polymer matrix. The three-dimensional structures can be removed to provide a plurality of holes in the polymer matrix. The plurality of holes can expose portions of the substrate. A layer of a metallic material can be deposited adjacent to the mask and exposed portions of the substrate. The mask can then be removed. The metallic material is then exposed to an oxidizing agent and an etchant to form holes or wires in the substrate.

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.

The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor.

A method includes forming a semiconductor fin on a semiconductor substrate, the semiconductor fin comprising germanium, silicon, silicon germanium or any of III-V elements; forming a mask layer on a top portion of the semiconductor fin; and trimming the semiconductor fin, wherein trimming the semiconductor fin comprises: immersing the semiconductor substrate in a first electrolyte bath; and laterally removing a first portion of the semiconductor fin by supplying a first voltage to a counter electrode in the electrolyte bath and a second voltage to the semiconductor substrate, wherein the second voltage is negative.

A method includes forming a semiconductor fin on a semiconductor substrate, the semiconductor fin comprising germanium, silicon, silicon germanium or any of III-V elements; forming a mask layer on a top portion of the semiconductor fin; and trimming the semiconductor fin, wherein trimming the semiconductor fin comprises: immersing the semiconductor substrate in a first electrolyte bath; and laterally removing a first portion of the semiconductor fin by supplying a first voltage to a counter electrode in the electrolyte bath and a second voltage to the semiconductor substrate, wherein the second voltage is negative.

Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.