Electrolytic Etching/Deposition System. A system for continuous circuit fabrication comprising means for storing and dispensing the substrate, means for laminating the substrate, means for printing the substrate, means for optical inspection of the substrate, means for photolithography of the substrate, means for drying the substrate, means for developing the substrate, means for washing the substrate and means for electroplating the substrate.

Electrolytic Etching/Deposition System. A system for continuous circuit fabrication comprising means for storing and dispensing the substrate, means for laminating the substrate, means for printing the substrate, means for optical inspection of the substrate, means for photolithography of the substrate, means for drying the substrate, means for developing the substrate, means for washing the substrate and means for electroplating the substrate.

Various technologies are described herein pertaining to electrochemical etching of a semiconductor controlled by way of a laser that emits light with an energy below a bandgap energy of the semiconductor.

Various technologies are described herein pertaining to electrochemical etching of a semiconductor controlled by way of a laser that emits light with an energy below a bandgap energy of the semiconductor.

An etcher comprises a bath, a plurality of blades, and a tunnel. The bath includes a first electrode at a first end and a second electrode at a second end. The plurality of blades is configured to fit in the bath. At least one blade of the plurality of blades holds a wafer. At least one tunnel is configured to fit between adjacent blades of the plurality of blades in the bath.

A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

Methods and apparatus for forming porous silicon layers are provided. In some embodiments, an anodizing bath includes: a housing having a first volume to hold a chemical solution; a cathode disposed within the first volume at a first side of the housing; an anode disposed within the first volume at a second side of the housing, opposite the first side, wherein a face of each of the cathode and the anode have a given surface area; a substrate holder configured to retain a plurality of substrates along a perimeter thereof within the first volume in a plurality of substrate holding positions, a plurality of vent openings fluidly coupled to the first volume to release process gases, wherein a top of each of the plurality of vent openings are disposed above a chemical solution fill level in the first volume.

Methods and apparatus for forming porous silicon layers are provided. In some embodiments, an anodizing bath includes: a housing having a first volume to hold a chemical solution; a cathode disposed within the first volume at a first side of the housing; an anode disposed within the first volume at a second side of the housing, opposite the first side, wherein a face of each of the cathode and the anode have a given surface area; a substrate holder configured to retain a plurality of substrates along a perimeter thereof within the first volume in a plurality of substrate holding positions, a plurality of vent openings fluidly coupled to the first volume to release process gases, wherein a top of each of the plurality of vent openings are disposed above a chemical solution fill level in the first volume.

A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.