A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.

A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.

Provided are a hole forming method and a hole forming apparatus capable of stably forming a single nanopore on a membrane. This hole forming method is a hole forming method for forming a hole in a film and includes: a first step of applying a first voltage between a first electrode and a second electrode, installed so as to sandwich the film provided in an electrolyte, and stopping the application of the first voltage when a current flowing between the first electrode and the second electrode reaches a first threshold current so as to form a thin film portion in a part of the film; and a second step of applying a second voltage between the first electrode and the second electrode after the first step so as to form a nanopore in the thin film portion.

Provided are a hole forming method and a hole forming apparatus capable of stably forming a single nanopore on a membrane. This hole forming method is a hole forming method for forming a hole in a film and includes: a first step of applying a first voltage between a first electrode and a second electrode, installed so as to sandwich the film provided in an electrolyte, and stopping the application of the first voltage when a current flowing between the first electrode and the second electrode reaches a first threshold current so as to form a thin film portion in a part of the film; and a second step of applying a second voltage between the first electrode and the second electrode after the first step so as to form a nanopore in the thin film portion.

The present disclosure relates to methods of fabricating a porous structure, such as a porous silicon carbide structure. The methods can include a step of providing a structure to be rendered porous, and a step of providing an etching solution. The methods can also include a step of electrochemically etching the structure to produce pores through at least a region of the structure, resulting in the formation of a porous structure. The morphology of the porous structure can be controlled by one or more parameters of the electrochemical etching process, such as the strength of the etching solution and/or the applied voltage.

An imprinting platform including a noble metal catalyst, a semiconductor substrate, and a pre-patterned polymer stamp, where the catalyst is attached to the stamp, and related methods and articles.

An imprinting platform including a noble metal catalyst, a semiconductor substrate, and a pre-patterned polymer stamp, where the catalyst is attached to the stamp, and related methods and articles.

The present disclosure provides an etching solution, including an ionic strength enhancer having an ionic strength greater than 10.sup.−3 M in the etching solution, wherein the ionic strength enhancer includes Li.sup.+, Na.sup.+, K.sup.+, Mg.sup.2+, Ca.sup.2+, N(CH.sub.3).sup.+, or N(C.sub.2H.sub.5).sup.4+, a solvent, and an etchant.

The present disclosure provides an etching solution, including an ionic strength enhancer having an ionic strength greater than 10.sup.−3 M in the etching solution, wherein the ionic strength enhancer includes Li.sup.+, Na.sup.+, K.sup.+, Mg.sup.2+, Ca.sup.2+, N(CH.sub.3).sup.+, or N(C.sub.2H.sub.5).sup.4+, a solvent, and an etchant.

A method, apparatus, and system for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.