H01L21/308

Radiation sensitive composition

A radiation sensitive composition including a siloxane polymer exhibiting phenoplast crosslinking reactivity as a base resin, which is excellent in resolution and can be used as a radiation sensitive composition capable of allowing a pattern having a desired-shape to be formed with sufficient precision. A radiation sensitive composition including as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof; and a photoacid generator, in which the hydrolyzable silane includes hydrolyzable silanes of Formula (1)
R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4-(a+b)  Formula (1)
wherein R.sup.1 is an organic group of Formula (1-2) ##STR00001##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.3 is a hydrolyzable group; and Formula (2)
R.sup.7.sub.cR.sup.8.sub.dSi(R.sup.9).sub.4-(c+d)  Formula (2)
wherein R.sup.7 is an organic group of Formula (2-1) ##STR00002##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.9 is a hydrolyzable group.

Apparatus for lithographically forming wafer identification marks and alignment marks

The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

PATTERNING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
20230230842 · 2023-07-20 ·

The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

Formation method of isolation feature of semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

METHOD AND SYSTEM FOR FABRICATING FIDUCIALS FOR PROCESSING OF SEMICONDUCTOR DEVICES

A method of forming alignment marks, each alignment mark including a plurality of fiducials, includes providing a III-V compound substrate having a device region and an alignment mark region. The method also includes forming a first hardmask in the device region and a hardmask structure in the alignment mark region, etching a first surface portion of the III-V compound substrate to form a plurality of trenches in the device region, and epitaxially regrowing a semiconductor layer in the trenches. The method further includes forming a second mask in the device region and a patterned structure in the alignment mark region. The patterned structure includes a set of masked regions corresponding to the plurality of fiducials and a second set of openings. The method also includes forming the plurality of fiducials.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
20230230841 · 2023-07-20 ·

A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.

PHOTORESIST COMPOSITIONS FOR EUV AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME
20230229083 · 2023-07-20 ·

Provided are photoresist compositions for EUV and methods for manufacturing a semiconductor device using the same. The photoresist compositions for EUV include a photosensitive resin, a photoacid generator, and an additive, wherein the additive comprises a copolymer including a first repeating unit that includes a fluoroalkyl group or hydrocarbon group substituted with one or more fluoroalkyl group(s), and a second repeating unit that includes a sulfonic acid group and an amide group.

PHOTORESIST COMPOSITIONS FOR EUV AND METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME
20230229083 · 2023-07-20 ·

Provided are photoresist compositions for EUV and methods for manufacturing a semiconductor device using the same. The photoresist compositions for EUV include a photosensitive resin, a photoacid generator, and an additive, wherein the additive comprises a copolymer including a first repeating unit that includes a fluoroalkyl group or hydrocarbon group substituted with one or more fluoroalkyl group(s), and a second repeating unit that includes a sulfonic acid group and an amide group.

Nanostructure featuring nano-topography with optimized electrical and biochemical properties

A method for forming a nanostructure includes coating an exposed surface of a base layer with a patterning layer. The method further includes forming a pattern in the patterning layer including nano-patterned non-random openings, such that a bottom portion of the non-random openings provides direct access to the exposed surface of the base layer. The method also includes depositing a material in the non-random openings in the patterning layer, such that the material contacts the exposed surface to produce repeating individually articulated nano-scale features. The method includes removing remaining portions of the patterning layer. The method further includes forming an encapsulation layer on exposed surfaces of the repeating individually articulated nanoscale features and the exposed surface of the base layer.