A sensor assembly for measuring a level of a liquid includes a measuring section through which a measuring current runs during operation of the sensor assembly and a temperature compensation section. The temperature compensation section compensates a temperature dependent variation of the measuring current within a predetermined operational temperature range.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor.

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.

A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

A circuit includes a first transistor, a second transistor and a first resistive load. The first transistor has a first terminal coupled to a first reference voltage terminal, a second terminal coupled to a second reference voltage terminal, and a control terminal coupled to the first reference voltage terminal. The second transistor has a first terminal coupled to the second reference voltage terminal, a second terminal coupled to the first reference voltage terminal and the control terminal of the first transistor, and a control terminal coupled to the second reference voltage terminal and the second terminal of the first transistor. The first transistor further comprises a third terminal coupled to the second reference voltage terminal through the first resistive load.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal layer, a gate, a drain, a source and a first doping region. The substrate has a first doping type. The metal layer is adjacent to the surface of the substrate. The gate is formed on the substrate. The drain is formed in the substrate and located at one side of the gate. The drain is adjacent to the metal layer. The source is formed in the substrate and located at another side of the gate. The first doping region is formed in the substrate and surrounds the metal layer and the drain. The first doping region has a second doping type. The second doping type is different from the first doping type.

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.