The disclosure provides a semiconductor device that can reduce the area of the circuit elements formed thereon. The semiconductor device includes a first conductivity type region formed on a substrate and formed with a resistance element surrounded by an insulating film; a second conductivity type region laminated in contact with an upper surface of the resistance element; a capacitor formed on the resistance element via an interlayer insulating layer; a via electrically connecting a terminal of the resistance element and a terminal of the capacitor in series; and a power supply line and a ground line electrically connected to the other terminal of the resistance element and the other terminal of the capacitor respectively.

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

A semiconductor device includes: a capacitor that includes a first metal plate; a capacitor dielectric layer disposed over the first metal plate; and a second metal plate disposed over the capacitor dielectric layer; and a resistor that includes a metal thin film, wherein the metal thin film of the resistor and the second metal plate of the capacitor are formed of a same metal material and wherein a top surface of the metal thin film is substantially coplanar with a top surface of the second metal plate of the capacitor.

A small-sized frequency-variable terahertz oscillator has a successive and large frequency-sweeping width even at a room temperature. The frequency-variable terahertz oscillator includes a slot antenna, a resonant tunneling diode and a varactor diode arranged parallel to each other along the slot antenna. The frequency-variable terahertz oscillator oscillates in a terahertz frequency range when the resonant tunneling diode and the varactor diode are separately applied with a direct voltage.

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

A resistor-capacitor component that includes: a capacitor having at least a first electrode structure and a second electrode structure separated by a dielectric structure; an insulating layer on the second electrode structure, the insulating layer having contact holes distributed across a surface of the insulating layer, each of the contact holes delimiting an opening onto the second electrode structure having a corrugated edge; and a conductive layer on the insulating layer and filling the contact holes to form electrical contacts with the second electrode structure.