The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.

The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.

A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of the semiconductor surface layer and a pair of matched devices in at least one of a CMOS area, BiCMOS area, bipolar transistor area, and a resistor area. Dopants are ion implanted into the at least one of the CMOS area, the BiCMOS area, the bipolar transistor area, and the resistor area. The substrate is annealed in a processing chamber of a rapid thermal processor (RTP). The annealing comprises an initial temperature stabilization step including first annealing at a lower temperature for a first time of at least 20 seconds, and then a second annealing comprising ramping from the lower temperature to a peak higher temperature that is at least 100 C. higher (>) than the lower temperature.

Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

An anti-fuse for a semiconductor device includes an electrode; a gate metal formed to extend from the electrode; a gate oxide layer formed under the gate metal; a semiconductor layer formed under the gate oxide layer to overlap with a center portion of the gate metal; and a first oxide layer formed under the gate metal and the gate oxide layer and on both sides of the semiconductor layer.

An e-fuse for a semiconductor device includes first and second electrodes; a gate metal electrically coupling the first and second electrodes with each other; a semiconductor layer formed under the gate metal, and forming a capacitor together with the gate metal; and a first oxide layer formed under the gate metal and on both sides of the semiconductor layer.

A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.

A semiconductor device includes: a drain electrode including a plurality of drain finger parts; a source electrode including a plurality of source finger parts and a Kelvin source part electrically connected with the source finger parts; a sense electrode positioned between a drain finger part and the Kelvin source part, which are next to each other in a particular direction; and a gate electrode positioned between a drain finger part and a source finger part, which are next to each other in the particular direction, and between a drain finger part and the sense electrode, which are next to each other in the particular direction. The sense electrode and the Kelvin source part are electrically connected via a sense resistance due to a spacing between the sense electrode and the Kelvin source part in the particular direction.

A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

An One-Time Programmable (OTP) memory is built in at least one of semiconductor fin structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one fin. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one fin can be built on a common well or on an isolated structure that has at least one MOS gate dividing fins into at least one first active region and a second active region.