It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured.

A laser polycrystallization apparatus including: a light source for emitting a laser beam; a diffraction grating for receiving the laser beam from the light source, changing a path and a magnitude of the received laser beam, and outputting the changed laser beam; a light split portion for splitting the laser beam received from the diffraction grating; and a light superposition portion for superposing the split laser beams received from the light split portion and irradiating the superposed split laser beams to a substrate. An angle between the laser beam irradiated to an incidence surface of the diffraction grating from the light source and a line substantially perpendicular to an emission surface of the diffraction grating is an acute angle.

A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a metal pattern positioned on the substrate; a buffer layer positioned on the metal pattern; and a semiconductor layer positioned on the buffer layer and including a source region, a channel region, and a drain region, wherein the metal pattern overlaps at least one of the source region and the drain region, and the metal pattern does not overlap the channel region.

A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.510.sup.20 atoms/cm.sup.3. A method of manufacturing the thin film transistor is also provided.

Embodiments of this disclosure provide a thin film of poly-silicon and a method for fabricating the same, and a thin film transistor and a method for fabricating the same, where a metal layer, a buffer layer, and an amorphous-silicon layer are formed on an underlying substrate successively, and metal atoms of the metal layer can be diffused to come into contact with the amorphous-silicon layer, so that the amorphous-silicon can be converted into a poly-silicon layer under the catalysis of the metal ions.

A method of forming a silicon film includes forming an amorphous, intrinsic, silicon layer on a substrate, forming a nickel pattern on the silicon layer, forming a first doped silicon region by doping phosphorus into a region of the silicon layer, and annealing to crystallize the silicon layer, the crystallization propagating by nickel induced lateral crystal growth starting from a portion of the silicon layer directly adjacent the nickel pattern on a first side of the first doped silicon region, propagating through the first doped silicon region to a second side of the first doped silicon region, and subsequently propagating to crystallize regions of the silicon layer to the second side of the first doped silicon region, the crystallization propagation through the first doped silicon region resulting in reduced nickel concentration, thereby forming a reduced nickel-concentration crystallized silicon layer to the second side of the first doped silicon region.

A method for manufacturing a TFT substrate is disclosed. The TFT substrate includes a drive TFT region and a display TFT region. The drive TFT region and the display TFT region are manufactured with different technologies, so that different requirements for TFT can be met. The manufacturing method according to the present disclosure mainly includes: forming a first amorphous silicon layer to obtain a drive TFT region; forming a second amorphous silicon layer to obtain a display TFT region; and then depositing a passivation layer and a flat layer, so that the TFT substrate is manufactured after following treatment steps.

A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a metal pattern positioned on the substrate; a buffer layer positioned on the metal pattern; and a semiconductor layer positioned on the buffer layer and including a source region, a channel region, and a drain region, wherein the metal pattern overlaps at least one of the source region and the drain region, and the metal pattern does not overlap the channel region.

Disclosed are a crystallization process of an oxide semiconductor, a method of manufacturing a thin film transistor including the same, a thin film transistor, a display panel, and an electronic device. The crystallization process of an oxide semiconductor includes forming an amorphous oxide semiconductor layer on a substrate, forming a crystallization auxiliary layer including a light absorbing inorganic material on the amorphous oxide semiconductor layer, and annealing the crystallization auxiliary layer to crystallize the amorphous oxide semiconductor layer.

It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured.