A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the device formation region, and an outer cathode region of a first conductivity type formed in the surface layer portion of the second principal surface of the semiconductor layer in the outer region.

Embodiments of the disclosure provide an insulated-gate bipolar transistor (IGBT), including: a substrate with a first type of doping; a drift region including a first semiconductor material and a second semiconductor material having dissimilar band gaps, the drift region having a second type of doping; and a base region with the first type of doping, wherein the drift region is disposed between the substrate and the base region; wherein a stoichiometry ratio of the first and second semiconductor materials of the drift region varies as a function of distance within the drift region to provide a built-in electric field via band gap modulation. The built-in electric field reduces a band gap barrier for minority charge carriers and increases a drift velocity of the minority charge carriers in the drift region, increasing a frequency response of the IGBT.

A semiconductor device includes: a high-concentration layer of a first conductivity-type provided on a drift layer of the first conductivity-type; a buried layer of a second conductivity-type provided in the high-concentration layer; an injection regulation region of the second conductivity-type provided on the high-concentration layer; a high-concentration region of the second conductivity-type provided inside the injection regulation region; a carrier supply region of the first conductivity-type provided at an upper part of the injection regulation region; and an insulated gate structure provided inside a trench, wherein a ratio of the impurity concentration of the injection regulation region to an impurity concentration of an upper part of the high-concentration layer is 0.5 or greater and 2 or smaller.

An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate below and adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A transistor cell includes a gate electrode and a source region of a first conductivity type. A drain/drift region is formed in a silicon carbide body. A buried region of the second conductivity type and the drain/drift region form a pn junction. The buried region and a well region form a unipolar junction. A mean net dopant density N.sub.2 of the buried region is higher than a mean net dopant density N.sub.1 of the well region. A first clamp region of the first conductivity type extends into the well region. A first low-resistive ohmic path electrically connects the first clamp region and the gate electrode. A second clamp region of the first conductivity type extends into the well region. A second low-resistive ohmic path electrically connects the second clamp region and the source region.

A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n.sup.−-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p.sup.+-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.

A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.

A semiconductor device includes an n-type base substrate; a p-type first region; a p-type surface region having a plurality of second corner portions and a plurality of second side portions surrounding the first region. The p-type surface region has a dopant concentration lower than a dopant concentration of the first region. The semiconductor device further includes a field plate in a region overlapping with the surface region in a plan view by way of an insulation film. The field plate has a plurality of field plate corner portions and a plurality of field plate side portions. A relationship of L1>L2 is established at least at a portion of the surface region or a relationship of FP1>FP2 is established at least at a portion of the field plate is satisfied. A withstand voltage of the second side portion is lower than a withstand voltage of the second corner portion.