A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

A semiconductor device includes: a chip having a main surface; a first conductive type first region formed on a surface layer portion of the main surface; a second conductive type second region formed on a surface layer portion of the first region; a drain region formed on a surface layer portion of the second region; a source region formed on the surface layer portion of the first region at a distance from the second region; and a second conductive type floating region formed in the first region at a thickness position between a bottom portion of the first region and a bottom portion of the second region and being spaced apart from the bottom portion of the second region, wherein the floating region faces the second region with a portion of the first region interposed between the floating region and the second region.

A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

A cell structure of a silicon carbide MOSFET device, comprising a first conductivity type drift region (3) located above a first conductivity type substrate (2). A main trench is provided in the surface of the first conductivity type drift region (3); a Schottky metal (4) is provided on the bottom and sidewalls of the main trench; a second conductivity type well region (7) is provided in the surface of the first conductivity type drift region (3) and around the main trench; a source region (8) is provided in the surface of the well region (7); a source metal (10) is provided above the source region (8); a gate insulating layer (6) and a gate (5) split into two parts are provided above the sides of the source region (8), the well region (7), and the first conductivity type drift region (3) close to the main trench.

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

An SBD of a JBS structure has on a front side of a semiconductor substrate, nickel silicide films in ohmic contact with p-type regions and a FLR, and a titanium film forming a Schottky junction with an n.sup.−-type drift region. A thickness of each of the nickel silicide films is in a range from 300 nm to 700 nm. The nickel silicide films each has a first portion protruding from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion protruding in the semiconductor substrate from the front surface of the semiconductor substrate in a depth direction. A thickness of the first portion is equal to a thickness of the second portion. A width of the second portion is wider than a width of the first portion.

A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region. In a plan view in a direction normal to the first main surface, the gate trench and the electric field relaxation region are disposed on a virtual line that extends in the first direction, and the connection region is in contact with the electric field relaxation region on the virtual line.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.