A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.

An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.

A silicon carbide semiconductor device includes a silicon carbide substrate having first and second main surfaces and including an electric field relaxation region and a connection region. A gate trench provided in the first main surface is defined by side surfaces and a bottom surface. The electric field relaxation region is a second conductivity type and provided between the bottom surface and the second main surface, and the connection region is the second conductivity type and electrically connects a contact region including first and second regions to the electric field relaxation region. In plan view, the gate trench and the electric field relaxation region are located on a virtual straight line. The first region is in contact with the connection region on the virtual straight line, and the second region is provided on a position where the source region is sandwiched between the gate trench and the second region.

A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.

A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

An amplifier circuit includes a first FET including a first semiconductor layer, a first source electrode, a first gate electrode, a first drain electrode and a first source wall having at least a part thereof provided above the first semiconductor layer between the first gate electrode and the first drain electrode, and a second FET including a second semiconductor layer, a second source electrode, a second gate electrode, a second drain electrode and a second source wall having at least a part thereof provided above the second semiconductor layer between the second gate electrode and the second drain electrode, wherein a length of the second source wall in a direction in which the second source electrode and the second drain electrode are arranged is smaller than that of the first source wall in a direction in which the first source electrode and the first drain electrode are arranged.

A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.